WIP: renesas_ra: Add (more) support for RA6M5 and RA2E1 #2164

desertsagebrush · 2025-11-11T21:35:20Z

Detailed description

Adding/expanding support for Renesas RA6M5, RA4M1, and RA2E1 microcontrollers.

Todo:

Add ID codes and confirm probe support
Implement flashing for MF4/MF3 flash on the RA2E1 (RV40 flash for the RA6M5 is already supported)
Handle RA4 MF3/4 flash gracefully (different block size)
Possibly support the OCDREG control registers hanging off of AP1 (APB-AP)

Your checklist for this pull request

I've read the Code of Conduct
I've read the guidelines for contributing to this repository
It builds for hardware native (see Building the firmware)
It builds as BMDA (see Building the BMDA)
I've tested it to the best of my ability
My commit messages provide a useful short description of what the commits do

Currently missing only write and erase. And testing. That's important.

desertsagebrush · 2025-11-24T20:38:05Z

Still todo:

Handle the different block size for RA4 flash
Update comments/etc to include the new RA family members
Handle the OCDREG AP?
Test more thoroughly
Possibly split the flash routines into their own files?
Possibly split the families into two feature flags to reduce the size burden?

dragonmux

Done a review - very happy with the general direction you're managing to take this, there are only a few fairly small details we spotted that could do with being cleaned up/sorted.

dragonmux · 2025-11-25T11:32:09Z

src/target/renesas_ra.c

 #define MF3_CF_BLOCK_SIZE       (0x800U)
-#define MF3_RA2A1_CF_BLOCK_SIZE (0x400U)
+#define MF3_RA2A1_CF_BLOCK_SIZE (0x400U) // Contradicted by RA2A1 Ref Manual
 #define MF3_DF_BLOCK_SIZE       (0x400U)
-#define MF3_CF_WRITE_SIZE       (0x40U)
+#define MF3_CF_WRITE_SIZE       (0x8U)
+#define MF3_RA2E1_CF_WRITE_SIZE (0x4U)
 #define MF3_DF_WRITE_SIZE       (0x1U)


We're aware this is, on your part, a "following the style set before", however the parens here are not doing anything useful and can (should) be dropped please. Their presence doesn't follow any of the rest of the code base.

dragonmux · 2025-11-25T11:59:00Z

src/target/renesas_ra.c

+	/* See "Switching to Code Flash P/E Mode": §35.13.3.2 of the RA2E1 manual R01UH0852EJ0170. */
+	/* Set PE/READ mode. Note that this is very similar to the RV40 mode control,
+	 * just with a different target register address. This probably ought to be
+	 * deduplicated, but getting it working is more important first


Having this duplicated is fine - often de-dupe attempts result in more complex/spaghetti code, so this is more than fine with us.

dragonmux · 2025-11-25T12:00:07Z

src/target/renesas_ra.c

+	 * implementation (i.e. ignoring FMS2) as that is what I have to test on
+	 * currently.
+	 *
+	 * Might also need a 5 us delay here (unlikely given the speed at which this


Please include a note of where exactly that 5µs delay might be needed as this may become relevant in the future. Otherwise, sound logic and reasoning 👍🏼

dragonmux · 2025-11-25T12:11:19Z

src/target/renesas_ra.c

+
+	if (!(target_mem32_read8(target, MF3_FSTATR1) & MF3_FSTATR1_FRDY) ||
+		target_mem32_read16(target, MF3_FENTRYR) != 0) {
+		DEBUG_WARN("flash is not ready, may be hanging mid unfinished command due to something going wrong, "


'Flash not 'flash please; this is a serious enough thing that we might suggest making it DEBUG_ERROR or, if possible to get it back through GDB at this moment in the protocol, a gdb_outf() call so the user definitely gets to see this.

dragonmux · 2025-11-25T12:14:08Z

src/target/renesas_ra.c

+		target_mem32_write16(target, MF3_FSARL, (const uint16_t)(addr & 0xffffU));
+		target_mem32_write16(target, MF3_FSARH, (const uint16_t)((addr >> 16) & 0xffffU));


The const's in these casts do nothing and can (should) be dropped. Casting to uint16_t likewise has the same value effect as masking by 0xffffU so the mask can technically be dropped (though having that explicit is no bad thing).

dragonmux · 2025-11-25T12:16:10Z

src/target/renesas_ra.c

+	/* Code flash or data flash operation */
+	const bool code_flash = addr < RENESAS_CF_END;
+
+	while (len) {


If it's possible to express this as a for loop over len, keeping len and addr constant, it would be better - the compiler's able to generate better code for this and prove to itself the correctness of the loop for optimisation purposes. Adding/tracking an offset turns out to be ~free due to instruction set things the compiler can take advantage of.

dragonmux · 2025-11-25T12:18:52Z

src/target/renesas_ra.c

+	target_mem32_write16(target, MF3_FSARL, (const uint16_t)(dest & 0xffffU));
+	target_mem32_write16(target, MF3_FSARH, (const uint16_t)((dest >> 16) & 0xffffU));
+
+	while (len) {


Same query here, especially as src could be cast to a buffer pointer so you only have one cast to uint8_t to do and then everything else already uses the right pointer width for the remainder

dragonmux · 2025-11-25T12:19:31Z

src/target/renesas_ra.c

+			target_mem32_write16(target, MF3_FWBL0, *(const uint16_t *)src);
+			target_mem32_write16(target, MF3_FWBH0, *((const uint16_t *)src + 1U));


((const uint16_t *)src)[0]/((const uint16_t *)src)[1] would we think be clearer here what you're intending to do.

renesas_ra: Add ID codes for RA6M5 and RA2E1

ee74377

dragonmux added this to the v2.1 release milestone Nov 11, 2025

dragonmux added Enhancement General project improvement New Target New debug target labels Nov 11, 2025

desertsagebrush added 8 commits November 18, 2025 16:17

renesas_ra: Add defines for MF3/4 flash

14ce499

renesas_ra: Add PNR enums for newer Renesas parts

808056e

fixup/renesas: Add RA4M1 ID code

96d150a

renesas_ra: Start implementing MF3 Flash support

fc563f7

renesas_ra: Further MF3/4 flash implementation

1c5c57f

Currently missing only write and erase. And testing. That's important.

renesas_ra: Add MF3 flash write implementation

567149a

renesas_ra: Add in block erase

3b1fbbd

renesas_ra: Add license attribution

5f81890

dragonmux reviewed Nov 25, 2025

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WIP: renesas_ra: Add (more) support for RA6M5 and RA2E1 #2164

WIP: renesas_ra: Add (more) support for RA6M5 and RA2E1 #2164

desertsagebrush commented Nov 11, 2025 •

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		target_mem32_write16(target, MF3_FSARL, (const uint16_t)(addr & 0xffffU));
		target_mem32_write16(target, MF3_FSARH, (const uint16_t)((addr >> 16) & 0xffffU));

		target_mem32_write16(target, MF3_FWBL0, (const uint16_t )src);
		target_mem32_write16(target, MF3_FWBH0, ((const uint16_t )src + 1U));

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WIP: renesas_ra: Add (more) support for RA6M5 and RA2E1 #2164

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WIP: renesas_ra: Add (more) support for RA6M5 and RA2E1 #2164

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desertsagebrush commented Nov 11, 2025 •

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desertsagebrush commented Nov 24, 2025 •

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