Various adjustments for Cheshire port.

[yvantor]

• Add .elf generation for all target memories (SPM, DRAM).
• Add rule to compile all available benchmarks in one shot.
• Fix _putchar defienition in riscv-tests/syscalls.c.
• Add error downgrade to warnings to compile Dhrystone with modern GCC versions.
• Fix README instruction.
• Offload on Genesys2. -> Debug printf issues (Coremark mainly + carriage return ignored).

[alex96295]

@yvantor can this be merged or do you want to handle the open TODO before?

[yvantor]

@yvantor can this be merged or do you want to handle the open TODO before?

@alex96295 sorry I have been a bit busy with paper submission in the past few weeks. We have changed office and I need to redo the FPGAs setup for testing, if you don't mind I would wait still a bit before merging so I can get back on the task :)

[alex96295]

@yvantor can this be merged or do you want to handle the open TODO before?

@alex96295 sorry I have been a bit busy with paper submission in the past few weeks. We have changed office and I need to redo the FPGAs setup for testing, if you don't mind I would wait still a bit before merging so I can get back on the task :)

Sure thing bro