A vulnerability was discovered in RISC-V Rocket-Chip v1.6...
Moderate severity
Unreviewed
Published
Nov 10, 2025
to the GitHub Advisory Database
•
Updated Nov 12, 2025
Description
Published by the National Vulnerability Database
Nov 10, 2025
Published to the GitHub Advisory Database
Nov 10, 2025
Last updated
Nov 12, 2025
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
References