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Draft Extension: Zalasr #141

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5 changes: 5 additions & 0 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1259,6 +1259,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zalasr", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
Expand Down Expand Up @@ -2409,6 +2410,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zmmul");
case INSN_CLASS_A:
return riscv_subset_supports (rps, "a");
case INSN_CLASS_ZALASR:
return riscv_subset_supports (rps, "zalasr");
case INSN_CLASS_ZAWRS:
return riscv_subset_supports (rps, "zawrs");
case INSN_CLASS_F:
Expand Down Expand Up @@ -2619,6 +2622,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _ ("m' or `zmmul");
case INSN_CLASS_A:
return "a";
case INSN_CLASS_ZALASR:
return "zalasr";
case INSN_CLASS_ZAWRS:
return "zawrs";
case INSN_CLASS_F:
Expand Down
12 changes: 12 additions & 0 deletions gas/testsuite/gas/riscv/zalasr-64.d
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@@ -0,0 +1,12 @@
#as: -march=rv64i_zalasr
#objdump: -dr

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+3405b52f[ ]+ld\.aq[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3605b52f[ ]+ld\.aqrl[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ac5b02f[ ]+sd\.rl[ ]+a2,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ec5b02f[ ]+sd\.aqrl[ ]+a2,\(a1\)
5 changes: 5 additions & 0 deletions gas/testsuite/gas/riscv/zalasr-64.s
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@@ -0,0 +1,5 @@
target:
ld.aq a0, (a1)
ld.aqrl a0, (a1)
sd.rl a2, (a1)
sd.aqrl a2, (a1)
20 changes: 20 additions & 0 deletions gas/testsuite/gas/riscv/zalasr.d
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@@ -0,0 +1,20 @@
#as: -march=rv32i_zalasr
#objdump: -dr

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+3405852f[ ]+lb\.aq[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3605852f[ ]+lb\.aqrl[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3405952f[ ]+lh\.aq[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3605952f[ ]+lh\.aqrl[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3405a52f[ ]+lw\.aq[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3605a52f[ ]+lw\.aqrl[ ]+a0,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ac5802f[ ]+sb\.rl[ ]+a2,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ec5802f[ ]+sb\.aqrl[ ]+a2,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ac5902f[ ]+sh\.rl[ ]+a2,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ec5902f[ ]+sh\.aqrl[ ]+a2,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ac5a02f[ ]+sw\.rl[ ]+a2,\(a1\)
[ ]+[0-9a-f]+:[ ]+3ec5a02f[ ]+sw\.aqrl[ ]+a2,\(a1\)
13 changes: 13 additions & 0 deletions gas/testsuite/gas/riscv/zalasr.s
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@@ -0,0 +1,13 @@
target:
lb.aq a0, (a1)
lb.aqrl a0, (a1)
lh.aq a0, (a1)
lh.aqrl a0, (a1)
lw.aq a0, (a1)
lw.aqrl a0, (a1)
sb.rl a2, (a1)
sb.aqrl a2, (a1)
sh.rl a2, (a1)
sh.aqrl a2, (a1)
sw.rl a2, (a1)
sw.aqrl a2, (a1)
26 changes: 26 additions & 0 deletions include/opcode/riscv-opc.h
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Expand Up @@ -2315,6 +2315,23 @@
#define MASK_C_NTL_S1 0xffff
#define MATCH_C_NTL_ALL 0x9016
#define MASK_C_NTL_ALL 0xffff
/* Zalasr instructions. */
#define MATCH_LB_AQ 0x3400002f
#define MASK_LB_AQ 0xfdf0707f
#define MATCH_LD_AQ 0x3400302f
#define MASK_LD_AQ 0xfdf0707f
#define MATCH_LH_AQ 0x3400102f
#define MASK_LH_AQ 0xfdf0707f
#define MATCH_LW_AQ 0x3400202f
#define MASK_LW_AQ 0xfdf0707f
#define MATCH_SB_RL 0x3a00002f
#define MASK_SB_RL 0xfa007fff
#define MATCH_SD_RL 0x3a00302f
#define MASK_SD_RL 0xfa007fff
#define MATCH_SH_RL 0x3a00102f
#define MASK_SH_RL 0xfa007fff
#define MATCH_SW_RL 0x3a00202f
#define MASK_SW_RL 0xfa007fff
/* Zawrs instructions. */
#define MATCH_WRS_NTO 0x00d00073
#define MASK_WRS_NTO 0xffffffff
Expand Down Expand Up @@ -3370,6 +3387,15 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1)
DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL)
DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1)
DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL)
/* Zalasr instructions. */
DECLARE_INSN(lb_aq, MATCH_LB_AQ, MASK_LB_AQ)
DECLARE_INSN(ld_aq, MATCH_LD_AQ, MASK_LD_AQ)
DECLARE_INSN(lh_aq, MATCH_LH_AQ, MASK_LH_AQ)
DECLARE_INSN(lw_aq, MATCH_LW_AQ, MASK_LW_AQ)
DECLARE_INSN(sb_aq, MATCH_SB_AQ, MASK_SB_AQ)
DECLARE_INSN(sd_aq, MATCH_SD_AQ, MASK_SD_AQ)
DECLARE_INSN(sh_aq, MATCH_SH_AQ, MASK_SH_AQ)
DECLARE_INSN(sw_aq, MATCH_SW_AQ, MASK_SW_AQ)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
Expand Down
1 change: 1 addition & 0 deletions include/opcode/riscv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -396,6 +396,7 @@ enum riscv_insn_class
INSN_CLASS_ZIHINTNTL_AND_C,
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZMMUL,
INSN_CLASS_ZALASR,
INSN_CLASS_ZAWRS,
INSN_CLASS_F_INX,
INSN_CLASS_D_INX,
Expand Down
18 changes: 18 additions & 0 deletions opcodes/riscv-opc.c
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Expand Up @@ -982,6 +982,24 @@ const struct riscv_opcode riscv_opcodes[] =
{"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
{"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },

/* Zalasr instructions. */
{"lb.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LB_AQ, MASK_LB_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"lb.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LB_AQ|MASK_RL, MASK_LB_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"lh.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LH_AQ, MASK_LH_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"lh.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LH_AQ|MASK_RL, MASK_LH_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"lw.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LW_AQ, MASK_LW_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_4_BYTE },
{"lw.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LW_AQ|MASK_RL, MASK_LW_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_4_BYTE },
{"ld.aq", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LD_AQ, MASK_LD_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_8_BYTE },
{"ld.aqrl", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LD_AQ|MASK_RL, MASK_LD_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_8_BYTE },
{"sb.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SB_RL, MASK_SB_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
{"sb.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SB_RL|MASK_AQ, MASK_SB_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
{"sh.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SH_RL, MASK_SH_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_2_BYTE },
{"sh.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SH_RL|MASK_AQ, MASK_SH_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_2_BYTE },
{"sw.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SW_RL, MASK_SW_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_4_BYTE },
{"sw.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SW_RL|MASK_AQ, MASK_SW_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_4_BYTE },
{"sd.rl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SD_RL, MASK_SD_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_8_BYTE },
{"sd.aqrl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SD_RL|MASK_AQ, MASK_SD_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_8_BYTE },

/* Zawrs instructions. */
{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
Expand Down