Unexpected splitnets -ports behavior after #5095 (name single bit arrays as arrays) #5166
Description
Version
On which OS did this happen?
Linux
Reproduction Steps
#5095 recently added the ability to treat single bit verilog arrays, i.e. wire x [0:0];, as multi bit arrays for the purposes of naming. However, this seems to not work how I'd expect for splitnets -ports.
test case TCL:
yosys verific -sv test_module.sv
yosys verific -import test_module
yosys splitnets -ports -format "__:"
yosys write_verilog out.v
test case SV:
module test_module (
a,
b,
x,
y
);
input logic [0:0] a;
output logic [0:0] b;
input logic [1:0] x;
output logic [1:0] y;
assign b = a;
assign y = x;
endmodule
Expected Behavior
Contents of out.v:
module test_module(b_0_, x_0_, x_1_, y_0_, y_1_, a_0_);
input a_0_;
wire a_0_;
output b_0_;
wire b_0_;
input x_0_;
wire x_0_;
input x_1_;
wire x_1_;
output y_0_;
wire y_0_;
output y_1_;
wire y_1_;
assign b = a;
endmodule
Actual Behavior
Contents of out.v:
module test_module(b, x_0_, x_1_, y_0_, y_1_, a);
input [0:0] a;
wire [0:0] a;
output [0:0] b;
wire [0:0] b;
input x_0_;
wire x_0_;
input x_1_;
wire x_1_;
output y_0_;
wire y_0_;
output y_1_;
wire y_1_;
assign b = a;
endmodule
Would it be possible for the [0:0] array ports to be split with the provided naming convention as well?