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Temp 01 #12

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0675801
cache added
Vaibtan Nov 19, 2023
9e4e5a0
additions
Vaibtan Nov 20, 2023
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16 changes: 10 additions & 6 deletions Simulator/include/LRU_cache.hpp
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
#ifndef CACHE_RISCV_H
#define CACHE_RISCV_H

#include "utils.hpp"
#include "membus.hpp"

#define MA 0xffffffff

Expand All @@ -14,6 +13,11 @@ SET_ADDR_WIDTH :: lg(SET_NUM) = lg(4) = 2
TAG_WIDTH :: ADDR_WIDTH - SET_WIDTH - OFFSET_WIDTH :: 32-3-5 :: 24 Bits
*/

u32 bin_pow(u32 __bs, u32 __exp);
u32 bin_to_val(std::string __s);
std::string val_to_bin(u32 __v, u32 __SZ);
std::string make_sz(std::string __s, u32 __SZ);


//UNIFIED_CLASS
class set_associative{
Expand All @@ -25,15 +29,15 @@ class set_associative{
std::vector<std::vector<std::vector<u32>>> data;
std::vector<int> count;
std::vector<bool> empty;

public:
set_associative(int assoc, int cache_line, int blk_SZ);
MEM_BUS* _bus;
set_associative(MEM_BUS* bus_memory,int assoc, int cache_line, int blk_SZ);
void __incre__();
std::optional<u32> cache_read(u32 byte_ADDR, u32 set_ADDR, u32 off);
u32 cache_read(u32 byte_ADDR, u32 set_ADDR, u32 off);
//off = bin_to_val(ADDR_STR.substr(32 - __lg(blk_SZ), __lg(blk_SZ)));
//set_addr = bin_to_val(ADDR_STR.substr(32 - __lg(blk_SZ) - __lg(c_l / assoc), __lg(c_l / assoc)));
//byte_addr = bin_to_val(ADDR_STR.substr(0, 32 - __lg(blk_SZ) - __lg(c_l / assoc)));

void cache_write(u32 byte_ADDR, u32 set_ADDR, u32 off, u32 _val);
void __print__();
};
Expand Down
21 changes: 15 additions & 6 deletions Simulator/include/membus.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
#define MEMBUS_H
#include "utils.hpp"
#include "memory.hpp"
#include "LRU_cache.hpp"

struct DATA_MEM_BUS {
struct RISC_DATA_mem* data_mem;
Expand All @@ -11,12 +12,20 @@ struct INSTR_MEM_BUS {
struct RISC_INSTR_mem* instr_mem;
};

u32 data_bus_ld(DATA_MEM_BUS* _bus, u32 addr, u32 size);
void data_bus_st(DATA_MEM_BUS* _bus, u32 addr, u32 size, u32 value);
DATA_MEM_BUS* data_bus_init(RISC_DATA_mem* data_mem);
struct MEM_BUS {
struct DATA_MEM_BUS* data_bus;
struct INSTR_MEM_BUS* instr_bus;
};

INSTR_MEM_BUS* instr_bus_init(INSTR_mem* mem);
DATA_MEM_BUS* data_bus_init(DATA_mem* mem);
MEM_BUS* mem_bus_init(DATA_MEM_BUS* d_bus,INSTR_MEM_BUS* i_bus);

u32 data_bus_ld(DATA_MEM_BUS* _bus, u32 addr, u32 size, set_associative cache);
void data_bus_st(DATA_MEM_BUS* _bus, u32 addr, u32 size, u32 value, set_associative cache);


u32 instr_bus_ld(INSTR_MEM_BUS* _bus, u32 addr, u32 size);
void instr_bus_st(INSTR_MEM_BUS* _bus, u32 addr, u32 size, u32 value);
INSTR_MEM_BUS* instr_bus_init(RISC_INSTR_mem* instr_mem);
u32 instr_bus_ld(INSTR_MEM_BUS* _bus, u32 addr, u32 size, set_associative cache);
void instr_bus_st(INSTR_MEM_BUS* _bus, u32 addr, u32 size, u32 value, set_associative cache);

#endif
8 changes: 4 additions & 4 deletions Simulator/src/LRU_cache.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,9 @@ string make_sz(string __s, u32 __SZ) {
return __res;
}

set_associative::set_associative(int __asc, int c_l, int blk_SZ)
{
set_associative::set_associative(MEM_BUS* bus_memory,int __asc, int c_l, int blk_SZ)
{
this->_bus = bus_memory;
this->assoc = __asc;
this->cache_line = c_l;
this->blk_SZ = blk_SZ;
Expand All @@ -59,7 +60,7 @@ void set_associative::__incre__(){
}
}

optional<u32> set_associative::cache_read(u32 byte_ADDR, u32 set_ADDR, u32 off) {
u32 set_associative::cache_read(u32 byte_ADDR, u32 set_ADDR, u32 off) {
__incre__();
REP(_z, 0, assoc) {
if (!empty[set_ADDR * assoc + _z] && tag[set_ADDR * assoc + _z] == byte_ADDR) {
Expand Down Expand Up @@ -116,7 +117,6 @@ void set_associative::__print__() {

if (_z % assoc == 0) { cout << endl; }
// differentiate between sets

cout << "##BLOCK## " << val_to_bin(tag[_z], 32 - __lg(blk_SZ) - __lg(cache_line / assoc)) << " ##DATA## : ";

REP(_j, 0, blk_SZ) { cout << data[_z / assoc][_z % assoc][_j] << " "; }
Expand Down