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feat: update project tt_um_pwm_block from AGS-L/AGS-C1
Commit: 7294fa1768b750670da53f587d7daf6fd56be158 Workflow: https://github.com/AGS-L/AGS-C1/actions/runs/17382605284
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projects/tt_um_pwm_block/commit_id.json

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{
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"app": "Tiny Tapeout ttihp25b 68e2a499",
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"repo": "https://github.com/AGS-L/AGS-C1",
4-
"commit": "01c254b947e365b6392d00628b6463da11136985",
5-
"workflow_url": "https://github.com/AGS-L/AGS-C1/actions/runs/17361554746",
4+
"commit": "7294fa1768b750670da53f587d7daf6fd56be158",
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"workflow_url": "https://github.com/AGS-L/AGS-C1/actions/runs/17382605284",
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"sort_id": 1756670821464,
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"openlane_version": "OpenLane2 3.0.0.dev23",
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"pdk_name": "IHP-Open-PDK",

projects/tt_um_pwm_block/docs/info.md

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@@ -27,13 +27,19 @@ These command values are sent over SPI to control the PWM peripheral:
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| `8'd6` | Disable PWM output |
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| `8'd7` | Enable PWM output |
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For operations other than `ENABLE_PWM` and `DISABLE_PWM`, the SPI command must be followed by **four data bytes**. These bytes represent the value to be written into the selected register (e.g., Compare Value, Prescaler, or Duty Cycle). The data is transmitted **least significant byte (LSB) first**, so the first byte on the SPI bus corresponds to bits `[7:0]` of the value, the second byte to bits `[15:8]`, and so on, up to the most significant byte.
30+
For operations other than `ENABLE_PWM` and `DISABLE_PWM`, the SPI command must be followed by **four data bytes**. These bytes represent the value to be written into the selected register (e.g., Compare Value, Prescaler, or Duty Cycle). The data is transmitted **least significant byte (LSB) first**, so the first byte on the SPI bus corresponds to bits `[7:0]` of the value, the second byte to bits `[15:8]`, and so on, up to the most significant byte.
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The SPI slave has a clock polarity of zero and clock phase of zero, CPOL=0 and CPHA=0.
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Override pins are present to test the functionality of the PWM module without having to use the SPI. When driven high, the pins set the counter value, prescaler, duty cycles, and enable signal of the PWM directly to a preset value. When all override pins are driven the output signal should be 10kHz 50% duty cycle on all 3 PWM output pins when ran at 25MHz.
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There are two input pins that set the output of a uio output pin to 0, 1, and Z. This is just to test functionality of tristating in tinytapeout.
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---
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## How to test
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Program counter value, and duty cycle registers over SPI by sending the proper command byte followed by 4 bytes to set the value of the register. Then send the enable pwm command byte to start the SPI. Outputs 3 to 7 indicate that the registers value is non zero. Bidirectional output 0 shows if the enable register is non zero. Or use the override pins present on the ui_in to test just the PWM.
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## External hardware

projects/tt_um_pwm_block/info.yaml

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Original file line numberDiff line numberDiff line change
@@ -19,37 +19,37 @@ project:
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source_files:
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- "tt_um_pwm_block.v"
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- "pwm.v"
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- "MemoryManager.v"
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- "RegisterFiles.v"
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- "SPI_Slave.v"
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# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
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# This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
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pinout:
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# Inputs
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ui[0]: ""
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ui[1]: ""
31-
ui[2]: ""
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ui[3]: ""
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ui[4]: ""
34-
ui[5]: ""
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ui[6]: ""
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ui[7]: ""
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ui[0]: "Sets Value of uio_out0"
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ui[1]: "High Z on uio_out0 - 1 for Z"
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ui[2]: "CV_override"
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ui[3]: "PS_override"
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ui[4]: "DC1_override"
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ui[5]: "DC2_override"
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ui[6]: "DC3_override"
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ui[7]: "EN_override"
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# Outputs
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uo[0]: "pwm_0"
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uo[1]: "pwm_1"
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uo[2]: "pwm_2"
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uo[3]: ""
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uo[4]: ""
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uo[5]: ""
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uo[6]: ""
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uo[7]: ""
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uo[3]: "CV_nonZero"
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uo[4]: "PS_nonZero"
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uo[5]: "DC1_nonZero"
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uo[6]: "DC2_nonZero"
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uo[7]: "DC3_nonZero"
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# Bidirectional pins
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uio[0]: ""
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uio[0]: "EN_nonZero"
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uio[1]: ""
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uio[2]: ""
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uio[3]: ""
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uio[3]: "High Z test Pin"
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uio[4]: "spi_clk"
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uio[5]: "miso"
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uio[6]: "mosi"

projects/tt_um_pwm_block/stats/metrics.csv

Lines changed: 93 additions & 91 deletions
Original file line numberDiff line numberDiff line change
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design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19999
169+
design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.0000176941
170+
design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000191924
171+
design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.00000938096
172+
design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000191924
173+
design_powergrid__voltage__worst,0.0000191924
174+
design_powergrid__voltage__worst__net:VPWR,1.19998
175+
design_powergrid__drop__worst,0.0000191924
176+
design_powergrid__drop__worst__net:VPWR,0.0000176941
177+
design_powergrid__voltage__worst__net:VGND,0.0000191924
178+
design_powergrid__drop__worst__net:VGND,0.0000191924
177179
ir__voltage__worst,1.1999999999999999555910790149937383830547332763671875
178-
ir__drop__avg,0.0000154000000000000016324615270679743161963415332138538360595703125
179-
ir__drop__worst,0.00002720000000000000046321453617270691438534413464367389678955078125
180+
ir__drop__avg,0.00000948000000000000071450657890270719008185551501810550689697265625
181+
ir__drop__worst,0.00001769999999999999994019540816569957542014890350401401519775390625
180182
magic__drc_error__count,0
181183
magic__illegal_overlap__count,0
182184
design__lvs_device_difference__count,0

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