|
1 | 1 | Metric,Value
|
2 | 2 | design__lint_error__count,0
|
3 | 3 | design__lint_timing_construct__count,0
|
4 |
| -design__lint_warning__count,3 |
| 4 | +design__lint_warning__count,1 |
5 | 5 | design__inferred_latch__count,0
|
6 |
| -design__instance__count,3220 |
7 |
| -design__instance__area,50095.6 |
| 6 | +design__instance__count,3563 |
| 7 | +design__instance__area,54604.4 |
8 | 8 | design__instance_unmapped__count,0
|
9 | 9 | synthesis__check_error__count,0
|
10 | 10 | design__max_slew_violation__count__corner:nom_fast_1p32V_m40C,0
|
11 | 11 | design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C,0
|
12 | 12 | design__max_cap_violation__count__corner:nom_fast_1p32V_m40C,0
|
13 |
| -power__internal__total,0.001724987872876227 |
14 |
| -power__switching__total,0.000730915111489594 |
15 |
| -power__leakage__total,0.0000011623465070442762 |
16 |
| -power__total,0.002457065274938941 |
17 |
| -clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,3.494758359396745 |
18 |
| -clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,3.9947584149078974 |
19 |
| -timing__hold__ws__corner:nom_fast_1p32V_m40C,0.10522222280200537 |
20 |
| -timing__setup__ws__corner:nom_fast_1p32V_m40C,15.16070512042645 |
| 13 | +power__internal__total,0.0012069565709680319 |
| 14 | +power__switching__total,0.0003108481760136783 |
| 15 | +power__leakage__total,9.505986895419483E-7 |
| 16 | +power__total,0.0015187554527074099 |
| 17 | +clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,3.52978500863587 |
| 18 | +clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,4.029785064147023 |
| 19 | +timing__hold__ws__corner:nom_fast_1p32V_m40C,0.10630868708463086 |
| 20 | +timing__setup__ws__corner:nom_fast_1p32V_m40C,13.983795850408102 |
21 | 21 | timing__hold__tns__corner:nom_fast_1p32V_m40C,0.0
|
22 | 22 | timing__setup__tns__corner:nom_fast_1p32V_m40C,0.0
|
23 | 23 | timing__hold__wns__corner:nom_fast_1p32V_m40C,0
|
24 | 24 | timing__setup__wns__corner:nom_fast_1p32V_m40C,0.0
|
25 | 25 | timing__hold_vio__count__corner:nom_fast_1p32V_m40C,0
|
26 |
| -timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.105222 |
| 26 | +timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.106309 |
27 | 27 | timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
|
28 | 28 | timing__setup_vio__count__corner:nom_fast_1p32V_m40C,0
|
29 |
| -timing__setup_r2r__ws__corner:nom_fast_1p32V_m40C,17.352791 |
| 29 | +timing__setup_r2r__ws__corner:nom_fast_1p32V_m40C,18.299959 |
30 | 30 | timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
|
31 | 31 | design__max_slew_violation__count__corner:nom_slow_1p08V_125C,0
|
32 | 32 | design__max_fanout_violation__count__corner:nom_slow_1p08V_125C,0
|
33 | 33 | design__max_cap_violation__count__corner:nom_slow_1p08V_125C,0
|
34 |
| -clock__skew__worst_hold__corner:nom_slow_1p08V_125C,3.110836565285168 |
35 |
| -clock__skew__worst_setup__corner:nom_slow_1p08V_125C,3.610836620796321 |
36 |
| -timing__hold__ws__corner:nom_slow_1p08V_125C,0.6141308746481564 |
37 |
| -timing__setup__ws__corner:nom_slow_1p08V_125C,13.902736244641646 |
| 34 | +clock__skew__worst_hold__corner:nom_slow_1p08V_125C,3.1991374899122356 |
| 35 | +clock__skew__worst_setup__corner:nom_slow_1p08V_125C,3.6991375454233886 |
| 36 | +timing__hold__ws__corner:nom_slow_1p08V_125C,0.5983737008586132 |
| 37 | +timing__setup__ws__corner:nom_slow_1p08V_125C,11.50777017361335 |
38 | 38 | timing__hold__tns__corner:nom_slow_1p08V_125C,0.0
|
39 | 39 | timing__setup__tns__corner:nom_slow_1p08V_125C,0.0
|
40 | 40 | timing__hold__wns__corner:nom_slow_1p08V_125C,0
|
41 | 41 | timing__setup__wns__corner:nom_slow_1p08V_125C,0.0
|
42 | 42 | timing__hold_vio__count__corner:nom_slow_1p08V_125C,0
|
43 |
| -timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.614131 |
| 43 | +timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.598374 |
44 | 44 | timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C,0
|
45 | 45 | timing__setup_vio__count__corner:nom_slow_1p08V_125C,0
|
46 |
| -timing__setup_r2r__ws__corner:nom_slow_1p08V_125C,13.902737 |
| 46 | +timing__setup_r2r__ws__corner:nom_slow_1p08V_125C,16.278835 |
47 | 47 | timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C,0
|
48 | 48 | design__max_slew_violation__count__corner:nom_typ_1p20V_25C,0
|
49 | 49 | design__max_fanout_violation__count__corner:nom_typ_1p20V_25C,0
|
50 | 50 | design__max_cap_violation__count__corner:nom_typ_1p20V_25C,0
|
51 |
| -clock__skew__worst_hold__corner:nom_typ_1p20V_25C,3.3464647555805085 |
52 |
| -clock__skew__worst_setup__corner:nom_typ_1p20V_25C,3.84646458904705 |
53 |
| -timing__hold__ws__corner:nom_typ_1p20V_25C,0.28540670634677884 |
54 |
| -timing__setup__ws__corner:nom_typ_1p20V_25C,14.837815840418314 |
| 51 | +clock__skew__worst_hold__corner:nom_typ_1p20V_25C,3.403835976089792 |
| 52 | +clock__skew__worst_setup__corner:nom_typ_1p20V_25C,3.903836031600945 |
| 53 | +timing__hold__ws__corner:nom_typ_1p20V_25C,0.2930013536949722 |
| 54 | +timing__setup__ws__corner:nom_typ_1p20V_25C,13.078202002642552 |
55 | 55 | timing__hold__tns__corner:nom_typ_1p20V_25C,0.0
|
56 | 56 | timing__setup__tns__corner:nom_typ_1p20V_25C,0.0
|
57 | 57 | timing__hold__wns__corner:nom_typ_1p20V_25C,0
|
58 | 58 | timing__setup__wns__corner:nom_typ_1p20V_25C,0.0
|
59 | 59 | timing__hold_vio__count__corner:nom_typ_1p20V_25C,0
|
60 |
| -timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.285407 |
| 60 | +timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.293001 |
61 | 61 | timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C,0
|
62 | 62 | timing__setup_vio__count__corner:nom_typ_1p20V_25C,0
|
63 |
| -timing__setup_r2r__ws__corner:nom_typ_1p20V_25C,16.079082 |
| 63 | +timing__setup_r2r__ws__corner:nom_typ_1p20V_25C,17.582928 |
64 | 64 | timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C,0
|
65 | 65 | design__max_slew_violation__count,0
|
66 | 66 | design__max_fanout_violation__count,0
|
67 | 67 | design__max_cap_violation__count,0
|
68 |
| -clock__skew__worst_hold,3.494758359396745 |
69 |
| -clock__skew__worst_setup,3.610836620796321 |
70 |
| -timing__hold__ws,0.10522222280200537 |
71 |
| -timing__setup__ws,13.902736244641646 |
| 68 | +clock__skew__worst_hold,3.52978500863587 |
| 69 | +clock__skew__worst_setup,3.6991375454233886 |
| 70 | +timing__hold__ws,0.10630868708463086 |
| 71 | +timing__setup__ws,11.50777017361335 |
72 | 72 | timing__hold__tns,0.0
|
73 | 73 | timing__setup__tns,0.0
|
74 | 74 | timing__hold__wns,0
|
75 | 75 | timing__setup__wns,0.0
|
76 | 76 | timing__hold_vio__count,0
|
77 |
| -timing__hold_r2r__ws,0.105222 |
| 77 | +timing__hold_r2r__ws,0.106309 |
78 | 78 | timing__hold_r2r_vio__count,0
|
79 | 79 | timing__setup_vio__count,0
|
80 |
| -timing__setup_r2r__ws,13.902737 |
| 80 | +timing__setup_r2r__ws,16.278835 |
81 | 81 | timing__setup_r2r_vio__count,0
|
82 | 82 | design__die__bbox,0.0 0.0 202.08 313.74
|
83 | 83 | design__core__bbox,2.88 3.78 199.2 309.96
|
84 | 84 | design__io,45
|
85 | 85 | design__die__area,63400.6
|
86 | 86 | design__core__area,60109.3
|
87 |
| -design__instance__count__stdcell,3220 |
88 |
| -design__instance__area__stdcell,50095.6 |
| 87 | +design__instance__count__stdcell,3563 |
| 88 | +design__instance__area__stdcell,54604.4 |
89 | 89 | design__instance__count__macros,0
|
90 | 90 | design__instance__area__macros,0
|
91 | 91 | design__instance__count__padcells,0
|
92 | 92 | design__instance__area__padcells,0
|
93 | 93 | design__instance__count__cover,0
|
94 | 94 | design__instance__area__cover,0
|
95 |
| -design__instance__utilization,0.833409 |
96 |
| -design__instance__utilization__stdcell,0.833409 |
| 95 | +design__instance__utilization,0.908419 |
| 96 | +design__instance__utilization__stdcell,0.908419 |
97 | 97 | design__rows,81
|
98 | 98 | design__rows:CoreSite,81
|
99 | 99 | design__sites,33129
|
100 | 100 | design__sites:CoreSite,33129
|
101 |
| -design__instance__count__class:inverter,175 |
102 |
| -design__instance__area__class:inverter,977.962 |
103 |
| -design__instance__count__class:sequential_cell,391 |
104 |
| -design__instance__area__class:sequential_cell,18445.2 |
105 |
| -design__instance__count__class:multi_input_combinational_cell,1860 |
106 |
| -design__instance__area__class:multi_input_combinational_cell,19151 |
| 101 | +design__instance__count__class:buffer,1 |
| 102 | +design__instance__area__class:buffer,7.2576 |
| 103 | +design__instance__count__class:inverter,97 |
| 104 | +design__instance__area__class:inverter,533.434 |
| 105 | +design__instance__count__class:sequential_cell,393 |
| 106 | +design__instance__area__class:sequential_cell,18539.5 |
| 107 | +design__instance__count__class:multi_input_combinational_cell,2222 |
| 108 | +design__instance__area__class:multi_input_combinational_cell,23315 |
107 | 109 | flow__warnings__count,1
|
108 | 110 | flow__errors__count,0
|
109 | 111 | design__power_grid_violation__count__net:VPWR,0
|
110 | 112 | design__power_grid_violation__count__net:VGND,0
|
111 | 113 | design__power_grid_violation__count,0
|
112 |
| -design__instance__count__class:timing_repair_buffer,712 |
113 |
| -design__instance__area__class:timing_repair_buffer,10799.3 |
| 114 | +design__instance__count__class:timing_repair_buffer,769 |
| 115 | +design__instance__area__class:timing_repair_buffer,11537.8 |
114 | 116 | timing__drv__floating__nets,0
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115 | 117 | timing__drv__floating__pins,0
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116 | 118 | design__instance__displacement__total,0
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117 | 119 | design__instance__displacement__mean,0
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118 | 120 | design__instance__displacement__max,0
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119 |
| -route__wirelength__estimated,82436.8 |
| 121 | +route__wirelength__estimated,106375 |
120 | 122 | design__violations,0
|
121 |
| -design__instance__count__class:clock_buffer,65 |
122 |
| -design__instance__area__class:clock_buffer,589.68 |
123 |
| -design__instance__count__class:clock_inverter,13 |
124 |
| -design__instance__area__class:clock_inverter,110.678 |
| 123 | +design__instance__count__class:clock_buffer,59 |
| 124 | +design__instance__area__class:clock_buffer,533.434 |
| 125 | +design__instance__count__class:clock_inverter,16 |
| 126 | +design__instance__area__class:clock_inverter,105.235 |
125 | 127 | design__instance__count__setup_buffer,0
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126 |
| -design__instance__count__hold_buffer,524 |
127 |
| -antenna__violating__nets,1 |
128 |
| -antenna__violating__pins,1 |
129 |
| -route__antenna_violation__count,1 |
130 |
| -antenna_diodes_count,4 |
131 |
| -design__instance__count__class:antenna_cell,4 |
132 |
| -design__instance__area__class:antenna_cell,21.7728 |
133 |
| -route__net,3608 |
| 128 | +design__instance__count__hold_buffer,547 |
| 129 | +antenna__violating__nets,2 |
| 130 | +antenna__violating__pins,2 |
| 131 | +route__antenna_violation__count,2 |
| 132 | +antenna_diodes_count,6 |
| 133 | +design__instance__count__class:antenna_cell,6 |
| 134 | +design__instance__area__class:antenna_cell,32.6592 |
| 135 | +route__net,3952 |
134 | 136 | route__net__special,2
|
135 |
| -route__drc_errors__iter:0,2198 |
136 |
| -route__wirelength__iter:0,93453 |
137 |
| -route__drc_errors__iter:1,1196 |
138 |
| -route__wirelength__iter:1,92380 |
139 |
| -route__drc_errors__iter:2,1102 |
140 |
| -route__wirelength__iter:2,92195 |
141 |
| -route__drc_errors__iter:3,140 |
142 |
| -route__wirelength__iter:3,91661 |
143 |
| -route__drc_errors__iter:4,52 |
144 |
| -route__wirelength__iter:4,91687 |
| 137 | +route__drc_errors__iter:0,2767 |
| 138 | +route__wirelength__iter:0,119568 |
| 139 | +route__drc_errors__iter:1,1520 |
| 140 | +route__wirelength__iter:1,118385 |
| 141 | +route__drc_errors__iter:2,1440 |
| 142 | +route__wirelength__iter:2,118224 |
| 143 | +route__drc_errors__iter:3,163 |
| 144 | +route__wirelength__iter:3,117483 |
| 145 | +route__drc_errors__iter:4,31 |
| 146 | +route__wirelength__iter:4,117483 |
145 | 147 | route__drc_errors__iter:5,8
|
146 |
| -route__wirelength__iter:5,91666 |
| 148 | +route__wirelength__iter:5,117479 |
147 | 149 | route__drc_errors__iter:6,0
|
148 |
| -route__wirelength__iter:6,91662 |
| 150 | +route__wirelength__iter:6,117458 |
149 | 151 | route__drc_errors,0
|
150 |
| -route__wirelength,91662 |
151 |
| -route__vias,21849 |
152 |
| -route__vias__singlecut,21849 |
| 152 | +route__wirelength,117458 |
| 153 | +route__vias,25387 |
| 154 | +route__vias__singlecut,25387 |
153 | 155 | route__vias__multicut,0
|
154 |
| -design__disconnected_pin__count,14 |
| 156 | +design__disconnected_pin__count,6 |
155 | 157 | design__critical_disconnected_pin__count,0
|
156 |
| -route__wirelength__max,584.11 |
157 |
| -timing__unannotated_net__count__corner:nom_fast_1p32V_m40C,420 |
| 158 | +route__wirelength__max,541.755 |
| 159 | +timing__unannotated_net__count__corner:nom_fast_1p32V_m40C,302 |
158 | 160 | timing__unannotated_net_filtered__count__corner:nom_fast_1p32V_m40C,0
|
159 |
| -timing__unannotated_net__count__corner:nom_slow_1p08V_125C,420 |
| 161 | +timing__unannotated_net__count__corner:nom_slow_1p08V_125C,302 |
160 | 162 | timing__unannotated_net_filtered__count__corner:nom_slow_1p08V_125C,0
|
161 |
| -timing__unannotated_net__count__corner:nom_typ_1p20V_25C,420 |
| 163 | +timing__unannotated_net__count__corner:nom_typ_1p20V_25C,302 |
162 | 164 | timing__unannotated_net_filtered__count__corner:nom_typ_1p20V_25C,0
|
163 |
| -timing__unannotated_net__count,420 |
| 165 | +timing__unannotated_net__count,302 |
164 | 166 | timing__unannotated_net_filtered__count,0
|
165 |
| -design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.19997 |
166 |
| -design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19998 |
167 |
| -design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.0000271591 |
168 |
| -design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000312087 |
169 |
| -design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.0000151556 |
170 |
| -design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000312087 |
171 |
| -design_powergrid__voltage__worst,0.0000312087 |
172 |
| -design_powergrid__voltage__worst__net:VPWR,1.19997 |
173 |
| -design_powergrid__drop__worst,0.0000312087 |
174 |
| -design_powergrid__drop__worst__net:VPWR,0.0000271591 |
175 |
| -design_powergrid__voltage__worst__net:VGND,0.0000312087 |
176 |
| -design_powergrid__drop__worst__net:VGND,0.0000312087 |
| 167 | +design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.19998 |
| 168 | +design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19999 |
| 169 | +design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.0000176941 |
| 170 | +design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000191924 |
| 171 | +design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.00000938096 |
| 172 | +design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000191924 |
| 173 | +design_powergrid__voltage__worst,0.0000191924 |
| 174 | +design_powergrid__voltage__worst__net:VPWR,1.19998 |
| 175 | +design_powergrid__drop__worst,0.0000191924 |
| 176 | +design_powergrid__drop__worst__net:VPWR,0.0000176941 |
| 177 | +design_powergrid__voltage__worst__net:VGND,0.0000191924 |
| 178 | +design_powergrid__drop__worst__net:VGND,0.0000191924 |
177 | 179 | ir__voltage__worst,1.1999999999999999555910790149937383830547332763671875
|
178 |
| -ir__drop__avg,0.0000154000000000000016324615270679743161963415332138538360595703125 |
179 |
| -ir__drop__worst,0.00002720000000000000046321453617270691438534413464367389678955078125 |
| 180 | +ir__drop__avg,0.00000948000000000000071450657890270719008185551501810550689697265625 |
| 181 | +ir__drop__worst,0.00001769999999999999994019540816569957542014890350401401519775390625 |
180 | 182 | magic__drc_error__count,0
|
181 | 183 | magic__illegal_overlap__count,0
|
182 | 184 | design__lvs_device_difference__count,0
|
|
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