added conversion for time and cap units for PDK 0.15

flow/designs/rapidus2hp/cva6/constraint.sdc

@@ -1,9 +1,16 @@
 # Derived from cva6_synth.tcl and Makefiles
 
+source $::env(PLATFORM_DIR)/util.tcl
+
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
 set clk_period 1125
-set input_delay 0.46
-set output_delay 0.11
+
+convert_time_value clk_period
+
+set input_delay [convert_time_value 0.46]
+set output_delay [convert_time_value 0.11]
+
+
 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

flow/designs/rapidus2hp/ethmac/constraint.sdc

@@ -1,7 +1,12 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 set top_clk_name wb_clk_i
 set clk_period 875
 set clk_io_pct 0.2
 set clk_port [get_ports $top_clk_name]
+
+convert_time_value clk_period
+
 create_clock -name $top_clk_name -period $clk_period $clk_port
 set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
 set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \
@@ -12,6 +17,9 @@ set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \
 set tx_clk_name mtx_clk_pad_i
 set tx_clk_port [get_ports $tx_clk_name]
 set tx_clk_period 300
+
+convert_time_value tx_clk_period
+
 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
 set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
   $tx_clk_port]
@@ -23,6 +31,9 @@ set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
 set rx_clk_name mrx_clk_pad_i
 set rx_clk_port [get_ports $rx_clk_name]
 set rx_clk_period 110
+
+convert_time_value rx_clk_period
+
 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
 set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
   $rx_clk_port]

flow/designs/rapidus2hp/gcd/constraint.sdc

@@ -1,10 +1,14 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 current_design gcd
 
 set clk_name core_clock
 set clk_port_name clk
 set clk_period 100
 set clk_io_pct 0.2
 
+convert_time_value clk_period
+
 set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port

flow/designs/rapidus2hp/hercules_idecode/prects.sdc

@@ -1,12 +1,16 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 #set sdc_version 2.1
 set sdc_version 1.4
 current_design hercules_idecode
 
 set clk_period 250
 
+convert_time_value clk_period
+
 set_max_fanout 32 [current_design]
-set_load 10 [all_outputs]
-set_max_capacitance 10 [all_inputs]
+set_load [convert_cap_value 10] [all_outputs]
+set_max_capacitance [convert_cap_value 10] [all_inputs]
 
 create_clock -name "clk" -add -period $clk_period \
   -waveform [list 0.0 [expr 0.5*$clk_period]] [get_ports clk]

flow/designs/rapidus2hp/hercules_is_int/prects.sdc

@@ -1,12 +1,16 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 #set sdc_version 2.1
 set sdc_version 1.4
 current_design hercules_is_int
 
 set clk_period 250
 
+convert_time_value clk_period
+
 set_max_fanout 32 [current_design]
-set_load 10 [all_outputs]
-set_max_capacitance 10 [all_inputs]
+set_load [convert_cap_value 10] [all_outputs]
+set_max_capacitance [convert_cap_value 10] [all_inputs]
 
 create_clock -name "clk" -add -period $clk_period \
   -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk]

flow/designs/rapidus2hp/hercules_is_int/prects_prop.sdc

@@ -1,12 +1,16 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 #set sdc_version 2.1
 set sdc_version 1.4
 current_design hercules_is_int
 
 set clk_period 250
 
+convert_time_value clk_period
+
 set_max_fanout 32 [current_design]
-set_load 10 [all_outputs]
-set_max_capacitance 10 [all_inputs]
+set_load [convert_cap_value 10] [all_outputs]
+set_max_capacitance [convert_cap_value 10] [all_inputs]
 
 create_clock -name "clk" -add -period $clk_period \
   -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk]

flow/designs/rapidus2hp/ibex/constraint.sdc

@@ -1,10 +1,14 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 set clk_name core_clock
 set clk_port_name clk_i
 set clk_period 590
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
 
+convert_time_value clk_period
+
 create_clock -name $clk_name -period $clk_period $clk_port
 
 set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc

@@ -1,8 +1,12 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 set clk_name core_clock
 set clk_port_name clk_i
 set clk_period 1468
 set clk_io_pct 0.2
 
+convert_time_value clk_period
+
 set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port

flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc

@@ -1,10 +1,14 @@
+source $::env(PLATFORM_DIR)/util.tcl
+
 current_design jpeg_encoder
 
 set clk_name clk
 set clk_port_name clk
 set clk_period 425
 set clk_io_pct 0.2
 
+convert_time_value clk_period
+
 set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port