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synth: Adjust verific port naming to match slang #3319

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Merged
merged 1 commit into from
Jul 16, 2025
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synth: Adjust verific port naming to match slang #3319

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1 change: 1 addition & 0 deletions flow/scripts/synth_preamble.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,7 @@ proc read_design_sources { } {
verific -vlog-define {*}$::env(VERILOG_DEFINES)
}
verific -sv2012 {*}$::env(VERILOG_FILES)
verific -import -no-split-complex-ports $::env(DESIGN_NAME)
} elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } {
verilog_defaults -push
if { [env_var_exists_and_non_empty VERILOG_DEFINES] } {
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