10-Bit Multi-Waveform Generator (Verilog)

A high-resolution waveform generator implemented in Verilog for FPGAs. This project uses a Finite State Machine (FSM) and a Look-Up Table (LUT) to generate four classic waveforms: Square, Triangle, Sawtooth, and Sine.

The output is designed to interface with a 10-bit R-2R Ladder DAC, providing 1,024 levels of analog amplitude resolution.

🚀 Features

• 10-bit Resolution: High-precision output for smooth analog signals.
• Multiple Waveforms: Toggle between Square, Triangle, Sawtooth, and Sine waves.
• ROM-based Sine Synthesis: Uses a 64-position Look-Up Table (LUT) for the sine wave.
• Hardware Agnostic: The core logic is written in standard Verilog, making it compatible with Xilinx, Altera (Intel), or Lattice FPGAs.

📊 Simulation Results

Below are the digital signal simulations for each waveform type:

Waveform	Simulation Preview
Sine
Square
Triangle
Sawtooth

---

🛠️ Hardware Implementation

Hardware Requirements

• FPGA Board: Tested on Spartan-6 (but compatible with any FPGA).
• DAC: R-2R Resistor Ladder (10 bits).
• Interface: 4 Input Buttons (Active Low) and 10 Digital Output Pins.

Circuit Preview

---

📐 How it Works

R-2R DAC Implementation

The 10-bit digital output (wave_out) is converted to an analog voltage using an R-2R ladder. The output voltage ($V_{out}$) follows the formula:

$$V_{out} = V_{ref} \times \frac{\text{Digital Value}}{1024}$$

Waveform Logic

• Square: Flips the output between 0 and 1023 based on the clock frequency.
• Sawtooth: A simple incremental counter that resets to 0 after reaching 1023.
• Triangle: Uses a directional flag (is_ascending) to increment until 1023 and then decrement back to 0.
• Sine: Uses a Phase Accumulator to index a 64-word ROM containing pre-calculated sine values.

🚀 Future Improvements

This project serves as a solid foundation for more complex signal processing. Potential upgrades include:

• Variable Frequency Control: Implementing a Phase Increment Register (Phase Tuning Word) to allow real-time frequency adjustment without changing the master clock.
• Amplitude Modulation: Adding a digital multiplier at the output to scale the waveform amplitude.
• Improved Filtering: Adding an active Low-Pass Filter (LPF) after the R-2R ladder to eliminate high-frequency quantization noise.