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[Analysis] Implement pipelined buffer dependency analysis#93

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JiaqiGuoSunlune wants to merge 3 commits intotilelang_mesh_mainfrom
u/jiaqiguo/pipelined_buffer_dependency
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[Analysis] Implement pipelined buffer dependency analysis#93
JiaqiGuoSunlune wants to merge 3 commits intotilelang_mesh_mainfrom
u/jiaqiguo/pipelined_buffer_dependency

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@JiaqiGuoSunlune JiaqiGuoSunlune commented Mar 15, 2026

Develop an analysis pass for buffer dependencies in T.Pipelined.

Buffers are grouped into two categories: 1) intra-iteration dependent (channel); and 2) inter-iteration dependent (state).

  • Intra-iteration means this buffer is produced and consumed in the same iteration
  • Inter-iteration means this buffer is produced in prev iterations but consumed in the current iteration

Inter-iteration dependent buffers are not allowed to be multi-versioned.

Basically, we first run a forward analysis for each statement in the loop body to identify those loop-carried buffer write, which means the buffer has new results when the iteration exits. Second, we run another round of forward analysis for each buffer read statement. If the read hits on loop-carried buffer write, then the buffer region is classified as inter-iteration dependent.

@JiaqiGuoSunlune JiaqiGuoSunlune changed the title Implement pipelined buffer dependency analysis [Analysis] Implement pipelined buffer dependency analysis Mar 15, 2026
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It's okay, but need to merge first.

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