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hw-mgmgt: kernel: patch: Add missing reset cause for NVL systems family
Add missing reset cause to mlx-platform driver for NVL systems family Added reset cause: "reset_sw_reset", "reset_cpu_thermal", "reset_aux_pwr_or_reload" Signed-off-by: Oleksandr Shamray <[email protected]>
1 parent ad54a42 commit d6ccdf5

6 files changed

+117
-81
lines changed

‎recipes-kernel/linux/linux-5.10/9005-platform-mellanox-Downstream-Introduce-support-of-Nv.patch‎

Lines changed: 43 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
From 3ae636735e2e2581a01bb855b547bdcaa5c07c78 Mon Sep 17 00:00:00 2001
1+
From 00006a6046fa2604cfea07d4e971ae3e10c900da Mon Sep 17 00:00:00 2001
22
From: Vadim Pasternak <[email protected]>
33
Date: Thu, 4 Jan 2024 07:40:04 +0000
4-
Subject: [PATCH 1/5] platform: mellanox: Downstream: Introduce support of
4+
Subject: [PATCH 3/7] platform: mellanox: Downstream: Introduce support of
55
Nvidia next genration L1 tray switch
66

77
Add support for new L1 tray switch node providing L1 connectivity for
@@ -17,11 +17,11 @@ of the all required platform driver.
1717
Signed-off-by: Oleksandr Shamray <[email protected]>
1818
Reviewed-by: Vadim Pasternak <[email protected]>
1919
---
20-
drivers/platform/mellanox/mlx-platform.c | 1125 ++++++++++++++++++++--
21-
1 file changed, 1025 insertions(+), 100 deletions(-)
20+
drivers/platform/mellanox/mlx-platform.c | 1143 ++++++++++++++++++++--
21+
1 file changed, 1043 insertions(+), 100 deletions(-)
2222

2323
diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
24-
index 4be0f29cc..f33aca457 100644
24+
index 4be0f29cc..3787dc8fb 100644
2525
--- a/drivers/platform/mellanox/mlx-platform.c
2626
+++ b/drivers/platform/mellanox/mlx-platform.c
2727
@@ -53,6 +53,7 @@
@@ -246,7 +246,7 @@ index 4be0f29cc..f33aca457 100644
246246
{
247247
.label = "erot1_recovery",
248248
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
249-
@@ -7012,139 +7151,675 @@ static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = {
249+
@@ -7012,139 +7151,693 @@ static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = {
250250
.counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data),
251251
};
252252

@@ -626,6 +626,12 @@ index 4be0f29cc..f33aca457 100644
626626
+ .mode = 0444,
627627
+ },
628628
+ {
629+
+ .label = "reset_sw_reset",
630+
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
631+
+ .mask = GENMASK(7, 0) & ~BIT(4),
632+
+ .mode = 0444,
633+
+ },
634+
+ {
629635
+ .label = "reset_pwr_button_or_leak_con",
630636
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
631637
+ .mask = GENMASK(7, 0) & ~BIT(5),
@@ -644,6 +650,18 @@ index 4be0f29cc..f33aca457 100644
644650
+ .mode = 0444,
645651
+ },
646652
+ {
653+
+ .label = "reset_cpu_thermal",
654+
+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
655+
+ .mask = GENMASK(7, 0) & ~BIT(0),
656+
+ .mode = 0444,
657+
+ },
658+
+ {
659+
+ .label = "reset_aux_pwr_or_reload",
660+
+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
661+
+ .mask = GENMASK(7, 0) & ~BIT(2),
662+
+ .mode = 0444,
663+
+ },
664+
+ {
647665
+ .label = "reset_comex_pwr_fail",
648666
+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
649667
+ .mask = GENMASK(7, 0) & ~BIT(3),
@@ -1018,7 +1036,7 @@ index 4be0f29cc..f33aca457 100644
10181036
.capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
10191037
},
10201038
};
1021-
@@ -7435,6 +8110,124 @@ static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = {
1039+
@@ -7435,6 +8128,124 @@ static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = {
10221040
.version = 1,
10231041
};
10241042

@@ -1143,15 +1161,15 @@ index 4be0f29cc..f33aca457 100644
11431161
/* Watchdog type1: hardware implementation version1
11441162
* (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
11451163
*/
1146-
@@ -7670,6 +8463,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
1164+
@@ -7670,6 +8481,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
11471165
case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
11481166
case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
11491167
case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
11501168
+ case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
11511169
case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
11521170
case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
11531171
case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1154-
@@ -7734,6 +8528,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
1172+
@@ -7734,6 +8546,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
11551173
case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
11561174
case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
11571175
case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
@@ -1160,7 +1178,7 @@ index 4be0f29cc..f33aca457 100644
11601178
case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
11611179
case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
11621180
case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
1163-
@@ -7755,6 +8551,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
1181+
@@ -7755,6 +8569,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
11641182
case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
11651183
case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
11661184
case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
@@ -1169,15 +1187,15 @@ index 4be0f29cc..f33aca457 100644
11691187
case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET:
11701188
return true;
11711189
}
1172-
@@ -7797,6 +8595,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1190+
@@ -7797,6 +8613,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
11731191
case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
11741192
case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
11751193
case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
11761194
+ case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
11771195
case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
11781196
case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
11791197
case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
1180-
@@ -7889,6 +8688,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1198+
@@ -7889,6 +8706,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
11811199
case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
11821200
case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
11831201
case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
@@ -1187,7 +1205,7 @@ index 4be0f29cc..f33aca457 100644
11871205
case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
11881206
case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
11891207
case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
1190-
@@ -7948,6 +8750,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1208+
@@ -7948,6 +8768,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
11911209
case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
11921210
case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
11931211
case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
@@ -1197,15 +1215,15 @@ index 4be0f29cc..f33aca457 100644
11971215
case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET:
11981216
return true;
11991217
}
1200-
@@ -7990,6 +8795,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1218+
@@ -7990,6 +8813,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
12011219
case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
12021220
case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
12031221
case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
12041222
+ case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
12051223
case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
12061224
case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
12071225
case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
1208-
@@ -8080,6 +8886,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1226+
@@ -8080,6 +8904,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
12091227
case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
12101228
case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
12111229
case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
@@ -1215,7 +1233,7 @@ index 4be0f29cc..f33aca457 100644
12151233
case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
12161234
case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
12171235
case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
1218-
@@ -8133,6 +8942,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1236+
@@ -8133,6 +8960,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
12191237
case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
12201238
case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
12211239
case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
@@ -1225,7 +1243,7 @@ index 4be0f29cc..f33aca457 100644
12251243
case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET:
12261244
return true;
12271245
}
1228-
@@ -8201,6 +9013,17 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = {
1246+
@@ -8201,6 +9031,17 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = {
12291247
MLXPLAT_CPLD_LPC_SM_SW_MASK },
12301248
};
12311249

@@ -1243,7 +1261,7 @@ index 4be0f29cc..f33aca457 100644
12431261
struct mlxplat_mlxcpld_regmap_context {
12441262
void __iomem *base;
12451263
};
1246-
@@ -8323,6 +9146,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = {
1264+
@@ -8323,6 +9164,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = {
12471265
.reg_write = mlxplat_mlxcpld_reg_write,
12481266
};
12491267

@@ -1264,7 +1282,7 @@ index 4be0f29cc..f33aca457 100644
12641282
/* Wait completion routine for indirect access for register map */
12651283
static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx)
12661284
{
1267-
@@ -8448,6 +9285,8 @@ static struct spi_board_info *mlxplat_spi;
1285+
@@ -8448,6 +9303,8 @@ static struct spi_board_info *mlxplat_spi;
12681286
static struct pci_dev *lpc_bridge;
12691287
static struct pci_dev *i2c_bridge;
12701288
static struct pci_dev *jtag_bridge;
@@ -1273,7 +1291,7 @@ index 4be0f29cc..f33aca457 100644
12731291

12741292
/* Platform default reset function */
12751293
static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused)
1276-
@@ -8480,6 +9319,26 @@ static void mlxplat_poweroff(void)
1294+
@@ -8480,6 +9337,26 @@ static void mlxplat_poweroff(void)
12771295
kernel_halt();
12781296
}
12791297

@@ -1300,7 +1318,7 @@ index 4be0f29cc..f33aca457 100644
13001318
static int __init mlxplat_register_platform_device(void)
13011319
{
13021320
mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1,
1303-
@@ -9011,6 +9870,38 @@ static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dm
1321+
@@ -9011,6 +9888,38 @@ static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dm
13041322
return mlxplat_register_platform_device();
13051323
}
13061324

@@ -1339,7 +1357,7 @@ index 4be0f29cc..f33aca457 100644
13391357
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
13401358
{
13411359
.callback = mlxplat_dmi_default_wc_matched,
1342-
@@ -9165,6 +10056,40 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
1360+
@@ -9165,6 +10074,40 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
13431361
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"),
13441362
},
13451363
},
@@ -1380,7 +1398,7 @@ index 4be0f29cc..f33aca457 100644
13801398
{
13811399
.callback = mlxplat_dmi_msn274x_matched,
13821400
.matches = {
1383-
@@ -9253,8 +10178,8 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
1401+
@@ -9253,8 +10196,8 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
13841402
int shift, i;
13851403

13861404
/* Scan adapters from expected id to verify it is free. */
@@ -1391,7 +1409,7 @@ index 4be0f29cc..f33aca457 100644
13911409
mlxplat_max_adap_num; i++) {
13921410
search_adap = i2c_get_adapter(i);
13931411
if (search_adap) {
1394-
@@ -9263,7 +10188,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
1412+
@@ -9263,7 +10206,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
13951413
}
13961414

13971415
/* Return if expected parent adapter is free. */
@@ -1400,7 +1418,7 @@ index 4be0f29cc..f33aca457 100644
14001418
return 0;
14011419
break;
14021420
}
1403-
@@ -9285,7 +10210,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
1421+
@@ -9285,7 +10228,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
14041422
}
14051423

14061424
/* Shift bus only if mux provided by 'mlxplat_mux_data'. */

‎recipes-kernel/linux/linux-5.10/9007-platform-mellanox-mlx-platform-Change-register-0x28-.patch‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
From f5e18518ee52c9f17d033fd2a3cc899558ba4e07 Mon Sep 17 00:00:00 2001
1+
From f6f41b1dddd256c9cf73ceda341fd08e2e34606f Mon Sep 17 00:00:00 2001
22
From: Felix Radensky <[email protected]>
33
Date: Mon, 13 Jan 2025 12:49:33 +0200
4-
Subject: [PATCH 4/5] platform: mellanox: mlx-platform: Change register 0x28
4+
Subject: [PATCH 6/7] platform: mellanox: mlx-platform: Change register 0x28
55
name
66

77
Register 0x28 was repurposed on new systems. Change its name
@@ -14,7 +14,7 @@ Reviewed-by: Vadim Pasternak <[email protected]>
1414
1 file changed, 3 insertions(+), 4 deletions(-)
1515

1616
diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
17-
index f33aca457..86a69e726 100644
17+
index 3787dc8fb..6b3bcf719 100644
1818
--- a/drivers/platform/mellanox/mlx-platform.c
1919
+++ b/drivers/platform/mellanox/mlx-platform.c
2020
@@ -53,7 +53,7 @@
@@ -26,15 +26,15 @@ index f33aca457..86a69e726 100644
2626
#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
2727
#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b
2828
#define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d
29-
@@ -8463,7 +8463,6 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
29+
@@ -8481,7 +8481,6 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
3030
case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
3131
case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
3232
case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
3333
- case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
3434
case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
3535
case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
3636
case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
37-
@@ -8595,7 +8594,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
37+
@@ -8613,7 +8612,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
3838
case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
3939
case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
4040
case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
@@ -43,7 +43,7 @@ index f33aca457..86a69e726 100644
4343
case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
4444
case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
4545
case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
46-
@@ -8795,7 +8794,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
46+
@@ -8813,7 +8812,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
4747
case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
4848
case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
4949
case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:

‎recipes-kernel/linux/linux-5.10/9008-platform-mellanox-mlx-platform-Add-support-for-Q3450.patch‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
From 5f6ff29baa69c7c22a711a6fe912725e49cea949 Mon Sep 17 00:00:00 2001
1+
From 2cf7d91f288ec50f17a990c4ddb04b860efe1bc4 Mon Sep 17 00:00:00 2001
22
From: Felix Radensky <[email protected]>
33
Date: Mon, 13 Jan 2025 17:40:59 +0200
4-
Subject: [PATCH 5/5] platform: mellanox: mlx-platform: Add support for
4+
Subject: [PATCH 7/7] platform: mellanox: mlx-platform: Add support for
55
Q3450-LD Nvidia XDR switch
66

77
Q3450-LD is XDR Infiniband CPO switch with 144 XDR ports, based on
@@ -24,7 +24,7 @@ Reviewed-by: Vadim Pasternak <[email protected]>
2424
1 file changed, 294 insertions(+)
2525

2626
diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
27-
index 86a69e726..b772709fd 100644
27+
index 6b3bcf719..8ef8c9121 100644
2828
--- a/drivers/platform/mellanox/mlx-platform.c
2929
+++ b/drivers/platform/mellanox/mlx-platform.c
3030
@@ -38,6 +38,7 @@
@@ -357,55 +357,55 @@ index 86a69e726..b772709fd 100644
357357
{
358358
.label = "leakage_status_clear",
359359
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
360-
@@ -8567,6 +8827,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
360+
@@ -8585,6 +8845,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
361361
case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
362362
case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:
363363
case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET:
364364
+ case MLXPLAT_CPLD_LPC_REG_CPLD7_VER_OFFSET:
365365
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
366366
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
367367
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
368-
@@ -8579,6 +8840,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
368+
@@ -8597,6 +8858,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
369369
case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
370370
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET:
371371
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET:
372372
+ case MLXPLAT_CPLD_LPC_REG_CPLD7_PN1_OFFSET:
373373
case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
374374
case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET:
375375
case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET:
376-
@@ -8713,6 +8975,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
376+
@@ -8731,6 +8993,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
377377
case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
378378
case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
379379
case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:
380380
+ case MLXPLAT_CPLD_LPC_REG_CPLD7_MVER_OFFSET:
381381
case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
382382
case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
383383
case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
384-
@@ -8767,6 +9030,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
384+
@@ -8785,6 +9048,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
385385
case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
386386
case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:
387387
case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET:
388388
+ case MLXPLAT_CPLD_LPC_REG_CPLD7_VER_OFFSET:
389389
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
390390
case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
391391
case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
392-
@@ -8779,6 +9043,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
392+
@@ -8797,6 +9061,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
393393
case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
394394
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET:
395395
case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET:
396396
+ case MLXPLAT_CPLD_LPC_REG_CPLD7_PN1_OFFSET:
397397
case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
398398
case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET:
399399
case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET:
400-
@@ -8905,6 +9170,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
400+
@@ -8923,6 +9188,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
401401
case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
402402
case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
403403
case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:
404404
+ case MLXPLAT_CPLD_LPC_REG_CPLD7_MVER_OFFSET:
405405
case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
406406
case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
407407
case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
408-
@@ -9825,6 +10091,27 @@ static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi)
408+
@@ -9843,6 +10109,27 @@ static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi)
409409
return mlxplat_register_platform_device();
410410
}
411411

@@ -433,7 +433,7 @@ index 86a69e726..b772709fd 100644
433433
static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi)
434434
{
435435
int i;
436-
@@ -10029,6 +10316,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
436+
@@ -10047,6 +10334,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
437437
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI159"),
438438
},
439439
},

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