RISC-V Neural Network Circuit Simulation Project

This is a simple neural network circuit simulation application implemented on RISC-V architecture, designed to run using QEMU RISC-V simulator.

Project Structure

riscv-neural-network/
├── include/
│   └── neural_network.h    # Neural network header file
├── src/
│   ├── main.c              # Main program
│   ├── neural_network.c    # Neural network implementation
│   ├── start.S             # RISC-V startup code
│   ├── simple_io.c         # Basic I/O functions
│   ├── printf.c            # Printf implementation
│   ├── simple_test.c       # Simple test version
│   ├── minimal_test.c      # Minimal test version
│   ├── ultra_simple.c      # Ultra simple test version
│   ├── baremetal_test.c    # Baremetal test version
│   ├── qemu_test.c         # QEMU test version
│   ├── start_simple.S      # Simple startup code
│   ├── start_standard.S    # Standard startup code
│   └── start_qemu.S        # QEMU startup code
├── build/                  # Compilation output directory
├── Makefile               # Build configuration
├── linker.ld              # Linker script
├── linker_simple.ld       # Simple linker script
├── linker_standard.ld     # Standard linker script
├── linker_qemu.ld         # QEMU linker script
├── riscv-pk/              # RISC-V Proxy Kernel source
└── README.md              # Documentation

Features

• Simple Neural Network Architecture: 2 input nodes → 3 hidden nodes → 1 output node
• Detailed Circuit Simulation: Step-by-step display of neural network computation
• RISC-V Native Execution: Runs directly on RISC-V instruction set
• No Standard Library Dependencies: Fully self-implemented math functions and I/O

Neural Network Architecture

Input Layer (2 nodes) → Hidden Layer (3 nodes) → Output Layer (1 node)

• Activation Function: Sigmoid
• Weight Initialization: Random initialization (-0.5 to 0.5)
• Bias: Random initialization (-0.1 to 0.1)

Build and Execution

Prerequisites

• RISC-V toolchain (riscv64-elf-gcc)
• QEMU RISC-V simulator (qemu-system-riscv64)

Build

make clean
make

Execution

# Run QEMU test version (RECOMMENDED)
make run-qemu

# Run main program with Spike simulator
make run

# Run simple test version
make run-simple

# Run minimal test version
make run-minimal

# Run ultra simple test version
make run-ultra

# Run standard test version
make run-standard

# Run with verbose output
make run-verbose
make run-simple-verbose
make run-minimal-verbose

# Or run directly with QEMU
qemu-system-riscv64 -machine virt -cpu rv64 -m 128M -kernel build/qemu_test.bin -nographic -serial stdio -monitor none

Other Commands

make disasm    # Generate disassembly file
make clean     # Clean build files
make help      # Show help

Code Description

Main Files

1. neural_network.h: Defines neural network data structures and function interfaces
2. neural_network.c: Implements neural network computation logic
3. main.c: Main program, tests different input combinations
4. start.S: RISC-V startup code, sets up stack and calls main
5. simple_io.c: Basic I/O functions for RISC-V
6. printf.c: Printf implementation without standard library

Core Functions

• init_neural_network(): Initialize neural network weights and biases
• forward_pass(): Forward propagation computation
• simulate_neural_circuit(): Detailed circuit simulation showing each computation step
• sigmoid(): Taylor series approximation of Sigmoid activation function

Test Cases

The program tests the following four input combinations:

1. [0.0, 0.0] → Output
2. [0.0, 1.0] → Output
3. [1.0, 0.0] → Output
4. [1.0, 1.0] → Output

Each test case displays:

• Network weights and biases
• Step-by-step computation process
• Final output results

Technical Details

• Instruction Set: RISC-V 64-bit (RV64GC)
• Memory Model: medany
• Floating Point: Software implementation (no hardware FPU)
• Math Functions: Self-implemented exp() Taylor series approximation

Current Status

✅ Completed

• Compilation: Successful, no errors
• Linking: Successful, generates executable
• Code Quality: Fixed all compilation warnings
• I/O Implementation: Basic printf and I/O functions implemented
• Memory Layout: Improved linker script and startup code with proper alignment
• System Calls: Enhanced system call interface with memory barriers
• Test Framework: Multiple test versions (simple_test.c, minimal_test.c, ultra_simple.c, qemu_test.c)
• Build System: Enhanced Makefile with multiple build targets
• RISC-V Execution: Successfully running on QEMU RISC-V simulator
• Memory Management: Proper memory mapping and alignment for RISC-V architecture
• Simulator Support: QEMU integration with OpenSBI bootloader

✅ Resolved Issues

• Spike Simulator Issues: Resolved by switching to QEMU RISC-V simulator
• Memory Access Faults: Fixed with proper memory layout and QEMU configuration
• Execution Environment: Successfully established working RISC-V execution environment
• Proxy Kernel Dependency: Bypassed by using QEMU's built-in OpenSBI support

🔧 Recent Fixes (Latest Update)

• QEMU Integration: Successfully integrated QEMU RISC-V simulator as primary execution environment
• Memory Layout: Created QEMU-specific linker script (linker_qemu.ld) with proper memory mapping
• Startup Code: Enhanced QEMU startup code (start_qemu.S) for OpenSBI compatibility
• Test Versions: Created comprehensive test suite including qemu_test.c for QEMU environment
• Build Targets: Added run-qemu target for easy QEMU execution
• Simulator Support: Established working RISC-V execution environment with OpenSBI v1.5.1

Notes

• This project is for educational purposes, implementing a simplified neural network
• Successfully running on QEMU RISC-V simulator with OpenSBI bootloader
• Math functions use approximation algorithms with limited precision
• QEMU provides a stable and reliable RISC-V execution environment

Future Improvements

• Add UART output functionality for better debugging and result display
• Implement GDB debugging support with QEMU
• Add performance benchmarking and profiling capabilities
• Implement more complex activation functions (ReLU, Tanh, etc.)
• Add backpropagation training functionality
• Support more neural network layers and architectures
• Implement complete printf functionality with format specifiers
• Add weight saving and loading functionality
• Create hardware-specific optimizations for real RISC-V hardware
• Add floating-point unit (FPU) support for better performance