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1. FPGA-CNN-accelerator-based-on-systolic-array FPGA-CNN-accelerator-based-on-systolic-array Public

   2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

   Verilog 219 13

2. buddy-compiler/buddy-mlir buddy-compiler/buddy-mlir Public

   An MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).

   C++ 678 223

3. JerryYin777/FPGA_Competition-RISC-V_Processor-in-PGL22G JerryYin777/FPGA_Competition-RISC-V_Processor-in-PGL22G Public

   FPGA Innovation Design Competition：RISC-V Processor-based Hardware and Software Design in PGL22G

   Verilog 12 3

4. pynq-kv260-dfx pynq-kv260-dfx Public

   Demos using kv260 and pynq to implement simple DFX(dynamic function exchange). Including DFX between add and sub,DFX between matrix multiplication and element-wise (dot) multiplication.

   Jupyter Notebook 1 1