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Added pre condition in the verilog module #620

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Added pre condition in the verilog module #620

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e6d9ae8
added pre condition in the verilog module
092vk Jun 29, 2025
c9f1518
fixed logic
092vk Aug 24, 2025
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23 changes: 14 additions & 9 deletions src/simulator/src/sequential/TflipFlop.js
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Original file line number Diff line number Diff line change
Expand Up @@ -146,18 +146,23 @@ export default class TflipFlop extends CircuitElement {
module TflipFlop(q, q_inv, clk, t, a_rst, pre, en);
parameter WIDTH = 1;
output reg [WIDTH-1:0] q, q_inv;
input clk, a_rst, pre, en;
input [WIDTH-1:0] t;
input clk, a_rst, en;
input [WIDTH-1:0] t, pre;

always @ (posedge clk or posedge a_rst)
always @ (posedge clk or posedge a_rst) begin
if (a_rst) begin
q <= 'b0;
q_inv <= 'b1;
end else if (en == 0) ;
else if (t) begin
q <= q ^ t;
q_inv <= ~q ^ t;
q <= pre;
q_inv <= ~pre;
end else if (en) begin
if (t) begin
// Toggle when T input is high
q <= ~q;
q_inv <= q;
end
// When t == 0, hold current state
end
Comment on lines +156 to 163
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@coderabbitai coderabbitai bot Aug 24, 2025

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🛠️ Refactor suggestion

⚠️ Potential issue

Fix multi-bit T semantics: use per-bit XOR instead of toggling all bits.

When WIDTH > 1, if (t) q <= ~q; flips all bits whenever any bit of t is 1. Simulator logic (Line 83) uses per-bit XOR (masterState = T ^ slaveState), so the Verilog must mirror that: q <= q ^ t; and keep q_inv complementary of the new q. This is a functional mismatch for vector widths and breaks correctness.

Apply this minimal fix:

-            end else if (en) begin
-              if (t) begin
-                // Toggle when T input is high
-                q <= ~q;
-                q_inv <= q;
-              end
-              // When t == 0, hold current state
-            end
+            end else if (en) begin
+              // Per-bit toggle: only bits with T=1 flip (matches simulator XOR semantics)
+              q     <= q ^ t;
+              q_inv <= ~q ^ t; // == ~(q ^ t), ensures q_inv remains the complement of new q
+            end
📝 Committable suggestion

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Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.

Suggested change
end else if (en) begin
if (t) begin
// Toggle when T input is high
q <= ~q;
q_inv <= q;
end
// When t == 0, hold current state
end
end else if (en) begin
// Per‐bit toggle: only bits with T=1 flip (matches simulator XOR semantics)
q <= q ^ t;
q_inv <= ~q ^ t; // == ~(q ^ t), ensures q_inv remains the complement of new q
end
🤖 Prompt for AI Agents 
In src/simulator/src/sequential/TflipFlop.js around lines 156-163, the code
toggles the entire vector when any bit of T is high; replace the scalar toggle
with per-bit XOR so multi-bit T works: set q <= q ^ t; and set q_inv to be the
bitwise complement of the resulting q (q_inv <= ~(q ^ t)) so q_inv remains the
complement of the updated q.

// When en == 0, hold current state
end
endmodule
`
}
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