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Generate Main for Simulation #50

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70385d0
Update for chipflow-lib shell support
robtaylor Jul 14, 2025
efe5eb4
Changes for port naming fixes in chipflow_lib
robtaylor Jul 15, 2025
0b5b6de
Log builds verbosely
robtaylor Jul 16, 2025
b1860d8
Use Sky130 drive mode
robtaylor Jul 16, 2025
d56faf5
Move example to Sky130 specific drive modes
robtaylor Jul 16, 2025
058c4e0
wip
robtaylor Jul 25, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/main.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ jobs:

- name: Submit to cloud backend
working-directory: ./${{ matrix.design }}
run: pdm run chipflow silicon submit --wait
run: pdm run chipflow -vv silicon submit --wait
env:
CHIPFLOW_API_KEY: ${{ secrets.CHIPFLOW_API_KEY}}

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31 changes: 0 additions & 31 deletions mcu_soc/chipflow.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -8,37 +8,6 @@ soc = "design.design:MySoC"
board = "design.steps.board:MyBoardStep"
software = "design.steps.software:MySoftwareStep"

[chipflow.clocks]
default = 'sys_clk'

[chipflow.resets]
default = 'sys_rst_n'

[chipflow.silicon]
process = "ihp_sg13g2"
package = "pga144"

[chipflow.silicon.pads]
# System
sys_clk = { type = "clock", loc = "114" }
sys_rst_n = { type = "reset", loc = "115" }

[chipflow.silicon.power]
dvss0 = { type = "power", loc = "1" }
dvdd0 = { type = "ground", loc = "9" }
vss0 = { type = "power", loc = "17" }
vdd0 = { type = "ground", loc = "25" }
dvss1 = { type = "power", loc = "33" }
dvdd1 = { type = "ground", loc = "41" }
vss1 = { type = "power", loc = "49" }
vdd1 = { type = "ground", loc = "57" }
dvss2 = { type = "power", loc = "65" }
dvdd2 = { type = "ground", loc = "73" }
vss2 = { type = "power", loc = "81" }
vdd2 = { type = "ground", loc = "89" }
dvss3 = { type = "power", loc = "97" }
dvdd3 = { type = "ground", loc = "105" }
vss3 = { type = "power", loc = "113" }
vdd3 = { type = "ground", loc = "121" }
dvss4 = { type = "power", loc = "129" }
dvdd4 = { type = "ground", loc = "137" }
30 changes: 15 additions & 15 deletions mcu_soc/design/sim/main.cc
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Expand Up @@ -14,21 +14,21 @@ using namespace cxxrtl_design;
int main(int argc, char **argv) {
p_sim__top top;

spiflash_model flash("flash", top.p_io_24_flash__clk_24_o, top.p_io_24_flash__csn_24_o,
top.p_io_24_flash__d_24_o, top.p_io_24_flash__d_24_oe, top.p_io_24_flash__d_24_i);
spiflash_model flash("flash", top.p_io_24_soc__flash__clk_24_o, top.p_io_24_soc__flash__csn_24_o,
top.p_io_24_soc__flash__d_24_o, top.p_io_24_soc__flash__d_24_oe, top.p_io_24_soc__flash__d_24_i);

uart_model uart_0("uart_0", top.p_io_24_uart__0__tx_24_o, top.p_io_24_uart__0__rx_24_i);
uart_model uart_1("uart_1", top.p_io_24_uart__1__tx_24_o, top.p_io_24_uart__1__rx_24_i);
uart_model uart_0("uart_0", top.p_io_24_soc__uart__0__tx_24_o, top.p_io_24_soc__uart__0__rx_24_i);
uart_model uart_1("uart_1", top.p_io_24_soc__uart__1__tx_24_o, top.p_io_24_soc__uart__1__rx_24_i);

gpio_model gpio_0("gpio_0", top.p_io_24_gpio__0__gpio_24_o, top.p_io_24_gpio__0__gpio_24_oe, top.p_io_24_gpio__0__gpio_24_i);
gpio_model gpio_1("gpio_1", top.p_io_24_gpio__1__gpio_24_o, top.p_io_24_gpio__1__gpio_24_oe, top.p_io_24_gpio__1__gpio_24_i);
gpio_model gpio_0("gpio_0", top.p_io_24_soc__gpio__0__gpio_24_o, top.p_io_24_soc__gpio__0__gpio_24_oe, top.p_io_24_soc__gpio__0__gpio_24_i);
gpio_model gpio_1("gpio_1", top.p_io_24_soc__gpio__1__gpio_24_o, top.p_io_24_soc__gpio__1__gpio_24_oe, top.p_io_24_soc__gpio__1__gpio_24_i);

spi_model spi_0("spi_0", top.p_io_24_user__spi__0__sck_24_o, top.p_io_24_user__spi__0__csn_24_o, top.p_io_24_user__spi__0__copi_24_o, top.p_io_24_user__spi__0__cipo_24_i);
spi_model spi_1("spi_1", top.p_io_24_user__spi__1__sck_24_o, top.p_io_24_user__spi__1__csn_24_o, top.p_io_24_user__spi__1__copi_24_o, top.p_io_24_user__spi__1__cipo_24_i);
spi_model spi_2("spi_2", top.p_io_24_user__spi__2__sck_24_o, top.p_io_24_user__spi__2__csn_24_o, top.p_io_24_user__spi__2__copi_24_o, top.p_io_24_user__spi__2__cipo_24_i);
spi_model spi_0("spi_0", top.p_io_24_soc__user__spi__0__sck_24_o, top.p_io_24_soc__user__spi__0__csn_24_o, top.p_io_24_soc__user__spi__0__copi_24_o, top.p_io_24_soc__user__spi__0__cipo_24_i);
spi_model spi_1("spi_1", top.p_io_24_soc__user__spi__1__sck_24_o, top.p_io_24_soc__user__spi__1__csn_24_o, top.p_io_24_soc__user__spi__1__copi_24_o, top.p_io_24_soc__user__spi__1__cipo_24_i);
spi_model spi_2("spi_2", top.p_io_24_soc__user__spi__2__sck_24_o, top.p_io_24_soc__user__spi__2__csn_24_o, top.p_io_24_soc__user__spi__2__copi_24_o, top.p_io_24_soc__user__spi__2__cipo_24_i);

i2c_model i2c_0("i2c_0", top.p_io_24_i2c__0__sda_24_oe, top.p_io_24_i2c__0__sda_24_i, top.p_io_24_i2c__0__scl_24_oe, top.p_io_24_i2c__0__scl_24_i);
i2c_model i2c_1("i2c_1", top.p_io_24_i2c__1__sda_24_oe, top.p_io_24_i2c__1__sda_24_i, top.p_io_24_i2c__1__scl_24_oe, top.p_io_24_i2c__1__scl_24_i);
i2c_model i2c_0("i2c_0", top.p_io_24_soc__i2c__0__sda_24_oe, top.p_io_24_soc__i2c__0__sda_24_i, top.p_io_24_soc__i2c__0__scl_24_oe, top.p_io_24_soc__i2c__0__scl_24_i);
i2c_model i2c_1("i2c_1", top.p_io_24_soc__i2c__1__sda_24_oe, top.p_io_24_soc__i2c__1__sda_24_i, top.p_io_24_soc__i2c__1__scl_24_oe, top.p_io_24_soc__i2c__1__scl_24_i);

cxxrtl::agent agent(cxxrtl::spool("spool.bin"), top);
if (getenv("DEBUG")) // can also be done when a condition is violated, etc
Expand All @@ -55,12 +55,12 @@ int main(int argc, char **argv) {
i2c_0.step(timestamp);
i2c_1.step(timestamp);

top.p_io_24_sys__clk_24_i.set(false);
top.p_io_24_clk_24_i.set(false);
agent.step();
agent.advance(1_us);
++timestamp;

top.p_io_24_sys__clk_24_i.set(true);
top.p_io_24_clk_24_i.set(true);
agent.step();
agent.advance(1_us);
++timestamp;
Expand All @@ -73,10 +73,10 @@ int main(int argc, char **argv) {
agent.step();
agent.advance(1_us);

top.p_io_24_sys__rst__n_24_i.set(false);
top.p_io_24_rst__n_24_i.set(false);
tick();

top.p_io_24_sys__rst__n_24_i.set(true);
top.p_io_24_rst__n_24_i.set(true);
for (int i = 0; i < 3000000; i++)
tick();

Expand Down
33 changes: 2 additions & 31 deletions minimal/chipflow.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -8,37 +8,8 @@ soc = "design.design:MySoC"
board = "design.steps.board:MyBoardStep"
software = "design.steps.software:MySoftwareStep"

[chipflow.clocks]
default = 'sys_clk'

[chipflow.resets]
default = 'sys_rst_n'

[chipflow.silicon]
process = "ihp_sg13g2"
package = "pga144"
process = "sky130"
package = "openframe"

[chipflow.silicon.pads]
# System
sys_clk = { type = "clock", loc = "114" }
sys_rst_n = { type = "reset", loc = "115" }

[chipflow.silicon.power]
dvss0 = { type = "power", loc = "1" }
dvdd0 = { type = "ground", loc = "9" }
vss0 = { type = "power", loc = "17" }
vdd0 = { type = "ground", loc = "25" }
dvss1 = { type = "power", loc = "33" }
dvdd1 = { type = "ground", loc = "41" }
vss1 = { type = "power", loc = "49" }
vdd1 = { type = "ground", loc = "57" }
dvss2 = { type = "power", loc = "65" }
dvdd2 = { type = "ground", loc = "73" }
vss2 = { type = "power", loc = "81" }
vdd2 = { type = "ground", loc = "89" }
dvss3 = { type = "power", loc = "97" }
dvdd3 = { type = "ground", loc = "105" }
vss3 = { type = "power", loc = "113" }
vdd3 = { type = "ground", loc = "121" }
dvss4 = { type = "power", loc = "129" }
dvdd4 = { type = "ground", loc = "137" }
21 changes: 15 additions & 6 deletions minimal/design/design.py
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,8 @@

from minerva.core import Minerva

from chipflow_lib.platforms import InputIOSignature, OutputIOSignature
from chipflow_lib.platforms import InputIOSignature, OutputIOSignature, BidirIOSignature, Sky130DriveMode
from chipflow_lib._signatures import GPIOSignature
# from .ips.pdm import PDMPeripheral

__all__ = ["MySoC"]
Expand All @@ -28,7 +29,8 @@ def __init__(self):
super().__init__({
"flash": Out(QSPIFlash.Signature()),
"uart_0": Out(UARTPeripheral.Signature()),
"gpio_0": Out(GPIOPeripheral.Signature(pin_count=8)),
"gpio_0": Out(GPIOSignature(pin_count=8)),
"gpio_open_drain": Out(GPIOSignature(pin_count=4, sky130_drive_mode=Sky130DriveMode.OPEN_DRAIN_STRONG_UP))
})

# Memory regions:
Expand All @@ -42,7 +44,7 @@ def __init__(self):
self.csr_base = 0xb0000000
self.csr_spiflash_base = 0xb0000000

self.csr_gpio_base = 0xb1000000
self.csr_gpio_base = 0xb1000000
self.csr_uart_base = 0xb2000000
self.csr_soc_id_base = 0xb4000000

Expand Down Expand Up @@ -98,11 +100,18 @@ def elaborate(self, platform):
m.submodules.sram = sram

# GPIOs
m.submodules.gpio = gpio = GPIOPeripheral(pin_count=8)
csr_decoder.add(gpio.bus, name="gpio_0", addr=self.csr_gpio_base - self.csr_base)
m.submodules.gpio0 = gpio0 = GPIOPeripheral(pin_count=8)
csr_decoder.add(gpio0.bus, name="gpio_0", addr=self.csr_gpio_base - self.csr_base)
sw.add_periph("gpio", "GPIO_0", self.csr_gpio_base)

connect(m, flipped(self.gpio_0), gpio.pins)
connect(m, flipped(self.gpio_0), gpio0.pins)

m.submodules.gpio_open_drain = gpio_open_drain = GPIOPeripheral(pin_count=4)
csr_decoder.add(gpio_open_drain.bus, name="gpio_open_drain", addr=self.csr_gpio_base + self.periph_offset - self.csr_base)
sw.add_periph("gpio", "GPIO_OPEN_DRAIN", self.csr_gpio_base + self.periph_offset)

connect(m, flipped(self.gpio_open_drain), gpio_open_drain.pins)


# UART
m.submodules.uart = uart = UARTPeripheral(init_divisor=int(25e6//115200), addr_width=5)
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16 changes: 8 additions & 8 deletions minimal/design/sim/main.cc
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Expand Up @@ -14,12 +14,12 @@ using namespace cxxrtl_design;
int main(int argc, char **argv) {
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I guess we no longer need to check in these files at all...

p_sim__top top;

spiflash_model flash("flash", top.p_io_24_flash__clk_24_o, top.p_io_24_flash__csn_24_o,
top.p_io_24_flash__d_24_o, top.p_io_24_flash__d_24_oe, top.p_io_24_flash__d_24_i);
spiflash_model flash("flash", top.p_io_24_soc__flash__clk_24_o, top.p_io_24_soc__flash__csn_24_o,
top.p_io_24_soc__flash__d_24_o, top.p_io_24_soc__flash__d_24_oe, top.p_io_24_soc__flash__d_24_i);

uart_model uart_0("uart_0", top.p_io_24_uart__0__tx_24_o, top.p_io_24_uart__0__rx_24_i);
uart_model uart_0("uart_0", top.p_io_24_soc__uart__0__tx_24_o, top.p_io_24_soc__uart__0__rx_24_i);

gpio_model gpio_0("gpio_0", top.p_io_24_gpio__0__gpio_24_o, top.p_io_24_gpio__0__gpio_24_oe, top.p_io_24_gpio__0__gpio_24_i);
gpio_model gpio_0("gpio_0", top.p_io_24_soc__gpio__0__gpio_24_o, top.p_io_24_soc__gpio__0__gpio_24_oe, top.p_io_24_soc__gpio__0__gpio_24_i);

cxxrtl::agent agent(cxxrtl::spool("spool.bin"), top);
if (getenv("DEBUG")) // can also be done when a condition is violated, etc
Expand All @@ -37,12 +37,12 @@ int main(int argc, char **argv) {

gpio_0.step(timestamp);

top.p_io_24_sys__clk_24_i.set(false);
top.p_io_24_clk_24_i.set(false);
agent.step();
agent.advance(1_us);
++timestamp;

top.p_io_24_sys__clk_24_i.set(true);
top.p_io_24_clk_24_i.set(true);
agent.step();
agent.advance(1_us);
++timestamp;
Expand All @@ -55,10 +55,10 @@ int main(int argc, char **argv) {
agent.step();
agent.advance(1_us);

top.p_io_24_sys__rst__n_24_i.set(false);
top.p_io_24_rst__n_24_i.set(false);
tick();

top.p_io_24_sys__rst__n_24_i.set(true);
top.p_io_24_rst__n_24_i.set(true);
for (int i = 0; i < 3000000; i++)
tick();

Expand Down
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