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1. ama-riscv ama-riscv Public

   SystemVerilog implementation of RISC-V RV32I_Zmmul & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verif…

   SystemVerilog 3

2. AES-256_UVM AES-256_UVM Public

   UVM testbench for AES-256 VHDL design with C model tied over DPI, golden NIST vectors, code & function coverage collection

   SystemVerilog 1

3. ama-riscv-sim ama-riscv-sim Public

   C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools

   C++ 5 2

4. AES-256_hardware_design AES-256_hardware_design Public

   VHDL design of the AES-256 encryption algorithm

   VHDL 1 1

5. Cyclone_II_SoPC Cyclone_II_SoPC Public

   VHDL hardware accelerators on Cyclone II FPGA with MCU apps in C for Nios II core

   C 4

6. LPC1768_development LPC1768_development Public

   CMSIS-RTOS2, driver development, and data acquisition application on NXP LPC1768

   C 2