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Preparing the launch#10

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luca-valente wants to merge 49 commits intomasterfrom
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Preparing the launch#10
luca-valente wants to merge 49 commits intomasterfrom
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@luca-valente luca-valente commented May 24, 2022

  • fix hier_icache ID width
  • bump to latest axi tag
  • connect mailbox interrupt to eu

Yvan Tortorella and others added 30 commits December 21, 2021 19:40
Extended cluster for VMM. TODO: fix width mismatch.
3f20069
Removed axi_slice dependency.
c1301bd
Modified Bender.yml for packages dependencies.
be2a974
Changed axi2mem.sv to axi2mem_cluster.sv and changed axi2mem Bender.
16b37d7
Modified Bender.yml and removed unused dependency modules.
0c2a8f6
Modified Bender.yml for cluster_interconnect dependency.
8df783a
Remodified Bender.yml for event unit and per2axi deps.
dca8cab
Remodified Bender.yml just for event unit.
b3a3ea6
Updated riscv core and fpu-interconnect
35d5596
Fixed width mismatch.
4407ca0
Fixed icache multiply driven.
0a54e3a
@luca-valente
Set default parameters as instatiation ones. For hierachical synth.
0d624e8
@luca-valente
Wrap tc_srams
8d6b752
@luca-valente
Tc_sram fix
039276c
@luca-valente
Increase FPU divsqrt latency to two cycles
ebc1a73
Updated event unit
cf88566
Added missing files in event_unit_flex.
2d838ab
Added misaligned input to tryx control register and updated riscv dep…
8702bbc 
…endency in Bender.yml.
@luca-valente
Increase FPU number to 8. 1 private per core. Reduce perf counters.
86f0495
@luca-valente
Rename the buses so the old one don't overwrite.
bd99c0b
Bender.yml pointing at new core.
7e6df69
Replaced fall-through register with spill register.
7863243
Modified fpu_interco in Bender.yml.
04c64fd
Removed useless comments and dismissed dependencies.
66d93b1
Changed XBAR latency mode and replaced spill register with axi cut.
4408a7c
@luca-valente
Add minor synthesis support.
4119cb1
@yvantor
Merge pull request #5 from AlSaqr-platform/synth_makefile
1fc8b51 
Add minor synthesis support.
Bender.yml point at new core and fpu_interco commits.
7660a0d
@yvantor
Merge pull request #4 from AlSaqr-platform/shaheendelivery
373acb8 
Shaheendelivery
Added fpu_interconnect master commit.
e0279a8
Yvan Tortorella and others added 19 commits February 2, 2022 11:49
Bumped common-cells
f89c9af
Updated axi2mem dependency.
7487c29
Merge branch 'bender-update' of github.com:AlSaqr-platform/pulp_clust…
21bbb90 
…er into bender-update
Updated axi2per dependency.
08ea637
Updated per2axi dependency
8f8bc8b
Removed local axi2X and per2axi dependencies and updated event unit d…
0d557b2 
…ependency.
Explicit memory map in pulp cluster package.
375b2a0
Removed local event unit and added remote dma.
94b71a9
Updated axi_to_mem commit
beacb26
Updated axi2per and per2axi commit
b87084d
Modified axi_to_mem in dmac_wrap
ace5d01
Fixed compilation warnings in amo_shim.
dc95486
Minor update to amo_shim
7cbbf74
Updated RISC-V and FPU interconnect dependencies.
cc1edd5
@luca-valente
Fix instruction cache AXI_ID width.
ed544c3
@luca-valente
Fix hier icache.
7978a2b
@luca-valente
Bump AXI to latest tag.
916804e
@luca-valente
Add mailbox_irq_i signal and connect to eu.
49d06c3
@luca-valente
Changed AXI4 port name to more general 'AXI2LITE'
a635280
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2 participants

@luca-valente @yvantor