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[aaelf64] Clarify relocation optimization [issue #328] #352

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[aaelf64] Clarify relocation optimization [issue #328] #352

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8 changes: 5 additions & 3 deletions aaelf64/aaelf64.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -1427,9 +1427,8 @@ Linkers may optionally optimize instructions affected by relocation. Relocation
- The relocations apply to consecutive instructions in the order specified.
- The relocations use the same symbol.
- The relocated instructions have the same source and destination register.
- The relocations do not appear separately or in a different order.

In this case each set of relocations is independent and may be optimized. The following sequences are defined:
The following sequences are defined:
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@smithp35 smithp35 Sep 18, 2025

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Line 1425 above (can't put the comment on the line). I suggest we insert a "base" before conditions
"if all the following base conditions are true."


- Large GOT indirection

Expand All @@ -1452,8 +1451,9 @@ Linkers may optionally optimize instructions affected by relocation. Relocation
- ``symbol`` does not have a ``st_shndx`` of ``SHN_ABS`` or the output is not required to be position independent.
- ``symbol`` is within range of the ``R_<CLS>_ADR_PREL_PG_HI21`` relocation.
- The addend of both relocations is zero.
- All ``R_<CLS>_ADR_GOT_PAGE`` and ``R_<CLS>_LD64_GOT_LO12_NC`` relocations to ``symbol`` are part of a sequence.
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@smithp35 smithp35 Sep 18, 2025

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I think this can be combined with the line below and removed from the specific conditions. For example

If the R_<CLS>_ADR_GOT_PAGE and R_<CLS>_LD64_GOT_LO12_NC relocations to symbol are used outside a sequence that satisfies the base conditions then the Large GOT indirection optimization is not legal for symbol.

Examples that prevent the Large GOT indirection optimization for symbol:

::

  // Different destination register
  ADRP  x0, :got: symbol            // R_<CLS>_ADR_GOT_PAGE
  LDR   x1, [x0 :got_lo12: symbol]  // R_<CLS>_LD64_GOT_LO12_NC

  // Instructions not in sequence.
  ADRP  x0, :got: symbol            // R_<CLS>_ADR_GOT_PAGE
  NOP
  LDR   x0, [x0 :got_lo12: symbol]  // R_<CLS>_LD64_GOT_LO12_NC

A linker may avoid creating a GOT entry if no other GOT relocations exist for the symbol.


The optimized sequence does not require a GOT entry. A linker may avoid creating a GOT entry if no other GOT relocations exist for the symbol.
If the GOT relocations are used outside of a valid sequence, the optimization is not legal (for that symbol). The optimized sequence does not require a GOT entry. A linker may avoid creating a GOT entry if no other GOT relocations exist for the symbol.

- PC-relative addressing

Expand All @@ -1469,6 +1469,8 @@ Linkers may optionally optimize instructions affected by relocation. Relocation
NOP
ADR x0, symbol // R_<CLS>_ADR_PREL_LO21

Each sequence is independent and may be optimized if in range.

Proxy-generating relocations
^^^^^^^^^^^^^^^^^^^^^^^^^^^^

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