@@ -40,6 +40,11 @@ static int32_t delete_cb(lv_draw_unit_t * draw_unit);
4040#if !LV_DRAW_DMA2D_ASYNC
4141 static bool check_transfer_completion (void );
4242#endif
43+
44+ #if defined(__ZEPHYR__ )
45+ static void lv_dma2d_isr_entry (const void * arg );
46+ #endif
47+
4348static void post_transfer_tasks (lv_draw_dma2d_unit_t * u );
4449
4550/**********************
@@ -82,19 +87,26 @@ void lv_draw_dma2d_init(void)
8287#else
8388#warning "LVGL can't enable the clock for DMA2D"
8489#endif
85-
8690 /* disable dead time */
8791 DMA2D -> AMTCR = 0 ;
8892
93+ #if defined(__ZEPHYR__ )
94+ IRQ_CONNECT (DMA2D_IRQn , 0 , lv_dma2d_isr_entry , NULL , 0 );
95+ irq_enable (DMA2D_IRQn );
96+ #else
8997 /* enable the interrupt */
9098 NVIC_EnableIRQ (DMA2D_IRQn );
99+ #endif
91100}
92101
93102void lv_draw_dma2d_deinit (void )
94103{
104+ #if defined(__ZEPHYR__ )
105+ irq_disable (DMA2D_IRQn );
106+ #else
95107 /* disable the interrupt */
96108 NVIC_DisableIRQ (DMA2D_IRQn );
97-
109+ #endif
98110 /* disable the DMA2D clock */
99111#if defined(STM32F4 ) || defined(STM32F7 ) || defined(STM32U5 ) || defined(STM32L4 )
100112 RCC -> AHB1ENR &= ~RCC_AHB1ENR_DMA2DEN ;
@@ -114,7 +126,7 @@ void lv_draw_dma2d_deinit(void)
114126}
115127
116128#if LV_USE_DRAW_DMA2D_INTERRUPT
117- void lv_draw_dma2d_transfer_complete_interrupt_handler (void )
129+ void lv_draw_dma2d_transfer_complete_interrupt_handler (void )
118130{
119131#if LV_DRAW_DMA2D_ASYNC
120132 lv_thread_sync_signal_isr (& g_unit -> interrupt_signal );
@@ -280,6 +292,17 @@ void lv_draw_dma2d_clean_cache(const lv_draw_dma2d_cache_area_t * mem_area)
280292 * STATIC FUNCTIONS
281293 **********************/
282294
295+ #if defined(__ZEPHYR__ )
296+ static void lv_dma2d_isr_entry (const void * arg )
297+ {
298+ LV_UNUSED (arg );
299+ #if LV_USE_DRAW_DMA2D_INTERRUPT
300+ lv_draw_dma2d_transfer_complete_interrupt_handler ();
301+ #endif
302+ }
303+ #endif
304+
305+
283306static int32_t evaluate_cb (lv_draw_unit_t * draw_unit , lv_draw_task_t * task )
284307{
285308 switch (task -> type ) {
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