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1 | 1 | from .insn import *
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2 |
| -from .variant import RV64I,Extensions |
| 2 | +from .variant import RV64I,Extensions,RV32IM |
3 | 3 |
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4 | 4 |
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5 | 5 | @isa("lui", opcode=0b0110111)
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@@ -333,14 +333,61 @@ class InstructionLD(InstructionIType):
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333 | 333 | class InstructionSD(InstructionISType):
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334 | 334 | pass
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335 | 335 |
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336 |
| - |
337 | 336 | @isa_pseudo()
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338 | 337 | class InstructionNOP(InstructionADDI):
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339 | 338 | def __init__(self):
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340 | 339 | super().__init__(0, 0, 0)
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341 | 340 | def __str__(self):
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342 | 341 | return "nop"
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343 | 342 |
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| 343 | +@isa("mul", opcode=0b0110011, funct3=0b000, funct7=0b0000001, variant=RV32IM) |
| 344 | +class InstructionMUL(InstructionRType): |
| 345 | + def execute(self, model: State): |
| 346 | + model.intreg[self.rd] = model.intreg[self.rs1] * model.intreg[self.rs2] |
| 347 | + |
| 348 | +@isa("mulh", opcode=0b0110011, funct3=0b001, funct7=0b0000001, variant=RV32IM) |
| 349 | +class InstructionMULH(InstructionRType): |
| 350 | + def execute(self, model: State): |
| 351 | + # TODO: implement |
| 352 | + pass |
| 353 | + |
| 354 | +@isa("mulhsu", opcode=0b0110011, funct3=0b010, funct7=0b0000001, variant=RV32IM) |
| 355 | +class InstructionMULHSU(InstructionRType): |
| 356 | + def execute(self, model: State): |
| 357 | + # TODO: implement |
| 358 | + pass |
| 359 | + |
| 360 | +@isa("mulhu", opcode=0b0110011, funct3=0b011, funct7=0b0000001, variant=RV32IM) |
| 361 | +class InstructionMULHU(InstructionRType): |
| 362 | + def execute(self, model: State): |
| 363 | + # TODO: implement |
| 364 | + pass |
| 365 | + |
| 366 | +@isa("div", opcode=0b0110011, funct3=0b100, funct7=0b0000001, variant=RV32IM) |
| 367 | +class InstructionDIV(InstructionRType): |
| 368 | + def execute(self, model: State): |
| 369 | + # TODO: implement |
| 370 | + pass |
| 371 | + |
| 372 | +@isa("divu", opcode=0b0110011, funct3=0b101, funct7=0b0000001, variant=RV32IM) |
| 373 | +class InstructionDIVU(InstructionRType): |
| 374 | + def execute(self, model: State): |
| 375 | + # TODO: implement |
| 376 | + pass |
| 377 | + |
| 378 | +@isa("rem", opcode=0b0110011, funct3=0b110, funct7=0b0000001, variant=RV32IM) |
| 379 | +class InstructionREM(InstructionRType): |
| 380 | + def execute(self, model: State): |
| 381 | + # TODO: implement |
| 382 | + pass |
| 383 | + |
| 384 | +@isa("remu", opcode=0b0110011, funct3=0b111, funct7=0b0000001, variant=RV32IM) |
| 385 | +class InstructionREMU(InstructionRType): |
| 386 | + def execute(self, model: State): |
| 387 | + # TODO: implement |
| 388 | + pass |
| 389 | + |
| 390 | + |
344 | 391 | @isaC("c.addi", 1, funct3=0b000)
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345 | 392 | class InstructionCADDI(InstructionCIType):
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346 | 393 | def expand(self):
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