fifo: renommage d'entite\n decode: une idee pour eliminer la trasition LINK\n build: petite correction:

Author: moyodiallo

Decod/decod.vhdl

@@ -148,10 +148,10 @@ end component;
 component fifo_127b
 	port(
 		din		: in std_logic_vector(126 downto 0);
-		dout		: out std_logic_vector(126 downto 0);
+		dout	: out std_logic_vector(126 downto 0);
 
 		-- commands
-		push		: in std_logic;
+		push	: in std_logic;
 		pop		: in std_logic;
 
 		-- flags
@@ -400,23 +400,23 @@ begin
 					empty		 => dec2exe_empty,
 					full		 => dec2exe_full,
 
-					reset_n	 => reset_n,
-					ck			 => ck,
-					vdd		 => vdd,
-					vss		 => vss);
+					reset_n	 	=> reset_n,
+					ck			=> ck,
+					vdd		 	=> vdd,
+					vss		 	=> vss);
 
 	dec2if : fifo_32b
-	port map (	din	=> reg_pc,
+	port map (		din		=> reg_pc,
 					dout	=> dec_pc,
 
-					push		 => dec2if_push,
-					pop		 => if_pop,
+					push	=> dec2if_push,
+					pop		=> if_pop,
 
-					empty		 => dec2if_empty,
-					full		 => dec2if_full,
+					empty	=> dec2if_empty,
+					full	=> dec2if_full,
 
 					reset_n	 => reset_n,
-					ck			 => ck,
+					ck		 => ck,
 					vdd		 => vdd,
 					vss		 => vss);
 
@@ -506,13 +506,13 @@ begin
 						 if_ir(31 downto 28) = X"9"	
 					else		  
 
-	reg_vv			when 	(if_ir(31 downto 28) = X"6" or		     
-							if_ir(31 downto 28) = X"7") 	
+	reg_vv			when 	if_ir(31 downto 28) = X"6" or		     
+							if_ir(31 downto 28) = X"7"
 					else
-	(reg_vv and reg_cznv) 	when 	(if_ir(31 downto 28) = X"A" or
+	(reg_vv and reg_cznv) 	when   	if_ir(31 downto 28) = X"A" or
 									if_ir(31 downto 28) = X"B" or
 									if_ir(31 downto 28) = X"C" or
-									if_ir(31 downto 28) = X"D") 	
+									if_ir(31 downto 28) = X"D"	
 					else '0';
 
 
@@ -582,7 +582,7 @@ begin
 
 	flag_wb	<= '1' 	when if_ir(24 downto 23) = '10' and regop_t = '1' --pour les TST, TEQ, CMP
 					else  if(20); --S (comme MOVS mis-a-jour du flag)
-
+ 
 -- reg read
 	-- Rn register
 	radr1 <= if_ir(15 down 12)	when mult_t = '1'
@@ -735,29 +735,86 @@ begin
 	case cur_state is
 
 	when FETCH =>
+		
 		debug_state <= X"1";
 		if2dec_pop <= '0';
 		dec2exe_push <= '0';
 		blink <= '0';
+		
 		mtrans_shift <= '0';
 		mtrans_loop_adr <= '0';
 
-		if dec2if_full = '0' and reg_pcv = '1' then
-		....
+		if dec2if_full = '1' and dec2if_empty = '0' then
+			next_state <= FETCH;
+		else if_pop = '1' then
+			next_state <= RUN;
+		else 
+			next_state <= FETCH;
 		end if;
 
 	when RUN =>
-			
-	when LINK =>
+		
+		mtrans_shift <= '0';
+		mtrans_loop_adr <= '0';
+
+		
+		dec2if_push <= '1' when reg_pcv      = '1' or 
+								dec2if_empty = '1' or
+								branch_t     = '0'    -- R14 <= PC+4 au prochain cycle
+							else 0;
+
+							\\ trans all like
+
+		-- si la fifo if2dec pas vide, donc on passe a l'inst suivante
+		if if2dec_empty = '0' then
+			if2dec_pop <= '1';
+		else 
+			if2dec_pop <= '0';
+		end if;
+		
+		-- on donne la main au prochain cycle horloge le EXEC
+		if condv = '0' or dec2exe_full = '1' then
+			dec2exe_push <= '0';
+		else if operv = '1' and condv = '1' and dec2exe_empty = '1' then
+			dec2exe_push <= 1;
+		end if;
+
+		-- on change de d'etat
+		if if2dec_empty = '1' or dec2exe_full = '1' or operv = '0' then
+			next_state <= RUN;
+		else if branch_t = '1' then
+			next_state <= BRANCH;
+		else if mtrans_t = '1' then
+			next_state <= MTRANS;
+		else 
+			next_state = RUN;
+		end if;
 
 	when BRANCH =>
+
+		mtrans_shift <= '0';
+		mtrans_loop_adr <= '0';
+
+		if reg_pcv = '1' then 
+			dec2if_push <= '1';
+		else 
+			dec2if_push <= '0';
+		end if;
+
+		if if2dec_empty = '1' then
+			next_state = BRANCH;
+		else if2dec_empty = '0' then
+			next_state <= RUN;
+		else 
+			next_state <= BRANCH;
+		end if;
 
 	when MTRANS =>
-	
-	
-
+		$$$ dec2exe_push <= '1';
+		if2dec_pop <= '0';
 
 	end case;
+
 end process;
 
 dec_pop <= if2dec_pop;

Fifo/fifo_127b.vhdl

@@ -1,7 +1,7 @@
 LIBRARY ieee;
 use ieee.std_logic_1164.all;
 
-ENTITY fifo IS
+ENTITY fifo_127b IS
 	PORT(
 		din		: in std_logic_vector(126 downto 0);
 		dout	: out std_logic_vector(126 downto 0);
@@ -19,9 +19,9 @@ ENTITY fifo IS
 		vdd		: in bit;
 		vss		: in bit
 	);
-END fifo;
+END fifo_127b;
 
-architecture dataflow of fifo is
+architecture dataflow of fifo_127b is
 
 signal fifo_d	: std_logic_vector(126 downto 0);
 signal fifo_v	: std_logic;

Fifo/fifo_32b.vhdl

@@ -1,7 +1,7 @@
 LIBRARY ieee;
 use ieee.std_logic_1164.all;
 
-ENTITY fifo IS
+ENTITY fifo_32b IS
 	PORT(
 		din		: in std_logic_vector(31 downto 0);
 		dout	: out std_logic_vector(31 downto 0);
@@ -19,9 +19,9 @@ ENTITY fifo IS
 		vdd		: in bit;
 		vss		: in bit
 	);
-END fifo;
+END fifo_32b;
 
-architecture dataflow of fifo is
+architecture dataflow of fifo_32b is
 
 signal fifo_d	: std_logic_vector(31 downto 0);
 signal fifo_v	: std_logic;

Fifo/fifo_72b.vhdl

@@ -1,7 +1,7 @@
 LIBRARY ieee;
 use ieee.std_logic_1164.all;
 
-ENTITY fifo IS
+ENTITY fifo_72b IS
 	PORT(
 		din		: in std_logic_vector(71 downto 0);
 		dout	: out std_logic_vector(71 downto 0);
@@ -19,9 +19,9 @@ ENTITY fifo IS
 		vdd		: in bit;
 		vss		: in bit
 	);
-END fifo;
+END fifo_72b;
 
-architecture dataflow of fifo is
+architecture dataflow of fifo_72b is
 
 signal fifo_d	: std_logic_vector(71 downto 0);
 signal fifo_v	: std_logic;

Ifetch/ifetch.vhdl

@@ -16,7 +16,7 @@ entity IFetch is
 			if_pop			: out Std_Logic;
 			dec_pc			: in Std_Logic_Vector(31 downto 0) ;
 
-			if_ir				: out Std_Logic_Vector(31 downto 0) ;
+			if_ir			: out Std_Logic_Vector(31 downto 0) ;
 			if2dec_empty	: out Std_Logic;
 			dec_pop			: in Std_Logic;
 
@@ -34,18 +34,18 @@ architecture Behavior OF IFetch is
 component fifo_32b
 	port(
 		din		: in std_logic_vector(31 downto 0);
-		dout		: out std_logic_vector(31 downto 0);
+		dout	: out std_logic_vector(31 downto 0);
 
 		-- commands
-		push		: in std_logic;
+		push	: in std_logic;
 		pop		: in std_logic;
 
 		-- flags
 		full		: out std_logic;
 		empty		: out std_logic;
 
 		reset_n	: in std_logic;
-		ck			: in std_logic;
+		ck		: in std_logic;
 		vdd		: in bit;
 		vss		: in bit
 	);

build.sh

@@ -1,9 +1,10 @@
+[ -d "build" ] && rm -fr build
 mkdir build
 cp Exec/exec.vhdl       build/exec.vhdl
 cp Makefile.txt         build/Makefile
 cp Ram/ram.vhdl         build/ram.vhdl
 cp Icache/icache.vhdl   build/icache.vhdl
-cp Dcache/dcache.vhdl   build/decache.vhdl
+cp Dcache/dcache.vhdl   build/dcache.vhdl
 cp Main/main_tb.vhdl    build/main_tb.vhdl
 cp Core/arm_core.vhdl   build/arm_core.vhdl
 cp Ifetch/ifetch.vhdl   build/ifetch.vhdl
@@ -15,5 +16,4 @@ cp Fifo/fifo_32b.vhdl   build/fifo_32b.vhdl
 cp ALU/alu.vhdl         build/alu.vhdl
 cp Shifter/shifter.vhdl build/shifter.vhdl
 cp Mem/mem.vhdl         build/mem.vhdl
-cd build
-echo "You can makefile and must have 'ghdl' command"
+echo "Do makefile in 'build' directory, you must have ghdl"