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Enabled BLIF buffer elimination in preparation for InOuts

lang-cppC/C++ codeC/C++ code

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

tests

VTR FlowVTR Design Flow (scripts/benchmarks/architectures)VTR Design Flow (scripts/benchmarks/architectures)

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1520

#1520 In verilog-to-routing/vtr-verilog-to-routing;

· djns99 opened on Sep 1, 2020

Converter from rr_nodes to RRGraph object

docsDocumentationDocumentation

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-pythonPython codePython code

libvtrutil

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

tests

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

VTR FlowVTR Design Flow (scripts/benchmarks/architectures)VTR Design Flow (scripts/benchmarks/architectures)

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1048

#1048 In verilog-to-routing/vtr-verilog-to-routing;

· tangxifan opened on Nov 15, 2019

Regression Tests should check average/geomean QoR metrics

no-staleExclude issue from being automatically marked as staleExclude issue from being automatically marked as stale

tests

VTR FlowVTR Design Flow (scripts/benchmarks/architectures)VTR Design Flow (scripts/benchmarks/architectures)

Status: Open.

#630 In verilog-to-routing/vtr-verilog-to-routing;

· kmurray opened on May 31, 2019

Improve VPR Regression Test Coverage

Good First IssueGood issues for new or first-time contributorsGood issues for new or first-time contributors

tests

VTR FlowVTR Design Flow (scripts/benchmarks/architectures)VTR Design Flow (scripts/benchmarks/architectures)

Status: Open.

#531 In verilog-to-routing/vtr-verilog-to-routing;

· kmurray opened on Apr 8, 2019