Closed as not planned
Description
Proposed Behaviour
The edge storage should be optimized for router behavior, which is driven by two concerns:
- Ability to iterate quickly (see https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/route/route_timing.cpp#L1984-L1986)
- Memory locality
The current allocation strategy has poor memory locality, and requires a pointer per node.
Current Behaviour
Currently rr graph edges are stored in per node allocations. This is a reasonable solution when edges are being mutated, but once edges are fixed (either after rr graph construction or if the rr graph is read from file) having one allocation be node is overly flexible.
Possible Solution
Assuming that during writing, node edges are only written and never read, and afterwards node edges are only read and never written, a two phase data structure can be used.