Fixed test vector

djns1 · djns1 · commit 4842b4b60dbf · 2020-06-30T14:46:22.000+12:00
diff --git a/ODIN_II/SRC/netlist_create_from_ast.cpp b/ODIN_II/SRC/netlist_create_from_ast.cpp
@@ -3164,7 +3164,6 @@ void terminate_registered_assignment(ast_node_t* always_node, signal_list_t* ass
                 }
             }
 
-            // TODO Does this variable need reset on each loop
             if (dependence_variable_position > -1) {
                 pin->net = list_dependence_pin[dependence_variable_position]->net;
             }
diff --git a/ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_input b/ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_input
@@ -1,4 +1,4 @@
-GLOBAL_SIM_BASE_CLK line_sel in1 in2
+GLOBAL_SIM_BASE_CLK dir out1 out2
 0 1 0 0
 0 1 0 1
 0 1 1 0
diff --git a/ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_output b/ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_output
@@ -1,9 +1,10 @@
-out
-0
-0
-1
-1
-0
-1
-0
-1
+out1 out2
+0 0
+0 0
+0 1
+0 1
+0 0
+1 1
+0 0
+1 1
+1 1

Original file line number	Diff line number	Diff line change
`@@ -3164,7 +3164,6 @@ void terminate_registered_assignment(ast_node_t* always_node, signal_list_t* ass`
`3164`	`3164`	`}`
`3165`	`3165`	`}`
`3166`	`3166`
`3167`		`- // TODO Does this variable need reset on each loop`
`3168`	`3167`	`if (dependence_variable_position > -1) {`
`3169`	`3168`	`pin->net = list_dependence_pin[dependence_variable_position]->net;`
`3170`	`3169`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-GLOBAL_SIM_BASE_CLK line_sel in1 in2`
	`1`	`+GLOBAL_SIM_BASE_CLK dir out1 out2`
`2`	`2`	`0 1 0 0`
`3`	`3`	`0 1 0 1`
`4`	`4`	`0 1 1 0`
-Original file line number
+Diff line change
@@ @@ -1,9 +1,10 @@ @@
 -out
 -0
 -0
 -1
 -1
 -0
 -1
 -0
 -1
 +out1 out2
 +0 0
 +0 0
 +0 1
 +0 1
 +0 0
 +1 1
 +0 0
 +1 1
 +1 1