From 5d7583fe1f947d3746dc9b66da38b62ba9902759 Mon Sep 17 00:00:00 2001 From: XiaolinZhao Date: Fri, 31 Jul 2026 09:41:50 +0800 Subject: [PATCH] cmd/internal/obj/loong64: add [X]VBITSELV and [X]VBITSELB instructions support Go asm syntax: VBITSELV VA, VK, VJ, VD XVBITSELV XA, XK, XJ, XD VBITSELB UI8, VJ, VD XVBITSELB UI8, XJ, XD Equivalent platform assembler syntax: vbitsel.v vd, vj, vk, va xvbitsel.v xd, xj, xk, xa vbitseli.b vd, vj, ui8 xvbitseli.b xd, xj, ui8 Change-Id: I76f6697f253ef8054ab5c433f125c3c06ea197a2 Reviewed-on: https://go-review.googlesource.com/c/go/+/808300 Reviewed-by: Meidan Li Reviewed-by: abner chenc LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com Reviewed-by: Cherry Mui Reviewed-by: Mark Freeman --- .../asm/internal/asm/testdata/loong64enc1.s | 8 +++++++ src/cmd/internal/obj/loong64/anames.go | 4 ++++ src/cmd/internal/obj/loong64/asm.go | 10 ++++++-- src/cmd/internal/obj/loong64/inst.go | 5 ++++ src/cmd/internal/obj/loong64/instOp.go | 24 +++++++++++-------- 5 files changed, 39 insertions(+), 12 deletions(-) diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index fa433d53e12134..85b7a56d254367 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -1422,6 +1422,14 @@ lable2: XVBITREVW $31, X2, X1 // 41fc1877 XVBITREVV $63, X2, X1 // 41fc1977 + // [X]{VBITSELV} instructions + VBITSELV V1, V2, V3, V4 // 6488100d + XVBITSELV X1, X2, X3, X4 // 6488200d + + // [X]{VBITSELB} instructions + VBITSELB $255, V2, V1 // 41fcc773 + XVBITSELB $0, X2, X1 // 4100c477 + // ALSL{W/WU/D} ALSLW $4, R4, R5, R6 // 86940500 ALSLWU $4, R4, R5, R6 // 86940700 diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go index 0244a8f9e58811..6c8756e1071ff0 100644 --- a/src/cmd/internal/obj/loong64/anames.go +++ b/src/cmd/internal/obj/loong64/anames.go @@ -813,5 +813,9 @@ var Anames = []string{ "XVSETALLNEH", "XVSETALLNEW", "XVSETALLNEV", + "VBITSELV", + "XVBITSELV", + "VBITSELB", + "XVBITSELB", "LAST", } diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go index 2ed2f23d11090a..7a78f5d2bcd9b1 100644 --- a/src/cmd/internal/obj/loong64/asm.go +++ b/src/cmd/internal/obj/loong64/asm.go @@ -1507,6 +1507,12 @@ func buildop(ctxt *obj.Link) { case AMOVF: opset(AMOVD, r0) + case AVSHUFB: + opset(AVBITSELV, r0) + + case AXVSHUFB: + opset(AXVBITSELV, r0) + case AMOVW, AMOVV, ARFE, @@ -1514,8 +1520,6 @@ func buildop(ctxt *obj.Link) { AJMP, AVMOVQ, AXVMOVQ, - AVSHUFB, - AXVSHUFB, AWORD, APRELD, APRELDX, @@ -1636,6 +1640,7 @@ func buildop(ctxt *obj.Link) { opset(AVEXTRINSH, r0) opset(AVEXTRINSW, r0) opset(AVEXTRINSV, r0) + opset(AVBITSELB, r0) // xvandi.b xd, xj, ui8 case AXVANDB: @@ -1653,6 +1658,7 @@ func buildop(ctxt *obj.Link) { opset(AXVEXTRINSH, r0) opset(AXVEXTRINSW, r0) opset(AXVEXTRINSV, r0) + opset(AXVBITSELB, r0) // vadd.b vd, vj, vk case AVADDB: diff --git a/src/cmd/internal/obj/loong64/inst.go b/src/cmd/internal/obj/loong64/inst.go index 3e9cd0c7dc4dba..0158f466fb5c07 100644 --- a/src/cmd/internal/obj/loong64/inst.go +++ b/src/cmd/internal/obj/loong64/inst.go @@ -944,6 +944,11 @@ const ( AXVSETALLNEW AXVSETALLNEV + AVBITSELV + AXVBITSELV + AVBITSELB + AXVBITSELB + ALAST // aliases diff --git a/src/cmd/internal/obj/loong64/instOp.go b/src/cmd/internal/obj/loong64/instOp.go index c2fa45ae573494..9ff497c50824e5 100644 --- a/src/cmd/internal/obj/loong64/instOp.go +++ b/src/cmd/internal/obj/loong64/instOp.go @@ -9,16 +9,18 @@ import ( ) var oprrrr = map[obj.As]uint32{ - AFMADDF: 0x81 << 20, // fmadd.s - AFMADDD: 0x82 << 20, // fmadd.d - AFMSUBF: 0x85 << 20, // fmsub.s - AFMSUBD: 0x86 << 20, // fmsub.d - AFNMADDF: 0x89 << 20, // fnmadd.f - AFNMADDD: 0x8a << 20, // fnmadd.d - AFNMSUBF: 0x8d << 20, // fnmsub.s - AFNMSUBD: 0x8e << 20, // fnmsub.d - AVSHUFB: 0x0d5 << 20, // vshuf.b - AXVSHUFB: 0x0d6 << 20, // xvshuf.b + AFMADDF: 0x81 << 20, // fmadd.s + AFMADDD: 0x82 << 20, // fmadd.d + AFMSUBF: 0x85 << 20, // fmsub.s + AFMSUBD: 0x86 << 20, // fmsub.d + AFNMADDF: 0x89 << 20, // fnmadd.f + AFNMADDD: 0x8a << 20, // fnmadd.d + AFNMSUBF: 0x8d << 20, // fnmsub.s + AFNMSUBD: 0x8e << 20, // fnmsub.d + AVSHUFB: 0xd5 << 20, // vshuf.b + AXVSHUFB: 0xd6 << 20, // xvshuf.b + AVBITSELV: 0xd1 << 20, // vbitsel.v + AXVBITSELV: 0xd2 << 20, // xvbitsel.v } var oprrr = map[obj.As]uint32{ @@ -906,6 +908,8 @@ var opirr = map[obj.As]uint32{ AXVBITREVH: 0x1dc6<<18 | 0x1<<14, // xvbitrevi.h AXVBITREVW: 0x1dc6<<18 | 0x1<<15, // xvbitrevi.w AXVBITREVV: 0x1dc6<<18 | 0x1<<16, // xvbitrevi.d + AVBITSELB: 0x1cf1 << 18, // vbitseli.b + AXVBITSELB: 0x1df1 << 18, // xvbitseli.b } var opirrr = map[obj.As]uint32{