diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index c5beac2a52..305fdd033f 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -90,6 +90,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LNL_ISHB, PCI_DID_INTEL_MTL_ISHB, PCI_DID_INTEL_ARL_ISHB, + PCI_DID_INTEL_ARP_S_ISHB, PCI_DID_INTEL_CNL_ISHB, PCI_DID_INTEL_CML_ISHB, PCI_DID_INTEL_TGL_ISHB, diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index a08417257a..79566954bc 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -85,6 +85,8 @@ #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 #define CPUID_ARROWLAKE_H_A0 0xc0652 +#define CPUID_ARROWLAKE_S_A0 0xc0660 +#define CPUID_ARROWLAKE_S_B0 0xc0662 #define CPUID_PANTHERLAKE_A0 0xc06c0 #define CPUID_SNOWRIDGE_A0 0x80660 #define CPUID_SNOWRIDGE_A1 0x80661 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 904add36e2..bb781dd141 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2183,6 +2183,7 @@ #define PCI_DID_INTEL_TGL_H_ISHB 0x43fc #define PCI_DID_INTEL_MTL_ISHB 0x7e45 #define PCI_DID_INTEL_ARL_ISHB 0x7745 +#define PCI_DID_INTEL_ARP_S_ISHB 0x7f78 #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 @@ -3145,6 +3146,70 @@ #define PCI_DID_INTEL_ARL_H_ESPI_0 0x7202 #define PCI_DID_INTEL_ARL_H_ESPI_1 0x7702 #define PCI_DID_INTEL_ARL_U_ESPI_0 0x7203 +#define PCI_DID_INTEL_ARL_S_ESPI_0 0xae00 +#define PCI_DID_INTEL_ARL_S_ESPI_1 0xae01 +#define PCI_DID_INTEL_ARL_S_ESPI_2 0xae02 +#define PCI_DID_INTEL_ARL_S_ESPI_3 0xae03 +#define PCI_DID_INTEL_ARL_S_ESPI_4 0xae04 +#define PCI_DID_INTEL_ARL_S_ESPI_5 0xae05 +#define PCI_DID_INTEL_ARL_S_ESPI_6 0xae06 +#define PCI_DID_INTEL_ARL_S_ESPI_7 0xae07 +#define PCI_DID_INTEL_ARL_S_ESPI_8 0xae08 +#define PCI_DID_INTEL_ARL_S_ESPI_9 0xae09 +#define PCI_DID_INTEL_ARL_S_ESPI_10 0xae0a +#define PCI_DID_INTEL_ARL_S_ESPI_11 0xae0b +#define PCI_DID_INTEL_ARL_S_ESPI_12 0xae0c +#define PCI_DID_INTEL_ARL_S_ESPI_13 0xae0d +#define PCI_DID_INTEL_ARL_S_ESPI_14 0xae0e +#define PCI_DID_INTEL_ARL_S_ESPI_15 0xae0f +#define PCI_DID_INTEL_ARL_S_ESPI_16 0xae10 +#define PCI_DID_INTEL_ARL_S_ESPI_17 0xae11 +#define PCI_DID_INTEL_ARL_S_ESPI_18 0xae12 +#define PCI_DID_INTEL_ARL_S_ESPI_19 0xae13 +#define PCI_DID_INTEL_ARL_S_ESPI_20 0xae14 +#define PCI_DID_INTEL_ARL_S_ESPI_21 0xae15 +#define PCI_DID_INTEL_ARL_S_ESPI_22 0xae16 +#define PCI_DID_INTEL_ARL_S_ESPI_23 0xae17 +#define PCI_DID_INTEL_ARL_S_ESPI_24 0xae18 +#define PCI_DID_INTEL_ARL_S_ESPI_25 0xae19 +#define PCI_DID_INTEL_ARL_S_ESPI_26 0xae1a +#define PCI_DID_INTEL_ARL_S_ESPI_27 0xae1b +#define PCI_DID_INTEL_ARL_S_ESPI_28 0xae1c +#define PCI_DID_INTEL_ARL_S_ESPI_29 0xae1d +#define PCI_DID_INTEL_ARL_S_ESPI_30 0xae1e +#define PCI_DID_INTEL_ARL_S_ESPI_31 0xae1f +#define PCI_DID_INTEL_ARP_S_ESPI_0 0x7f00 +#define PCI_DID_INTEL_ARP_S_ESPI_1 0x7f01 +#define PCI_DID_INTEL_ARP_S_ESPI_2 0x7f02 +#define PCI_DID_INTEL_ARP_S_ESPI_3 0x7f03 +#define PCI_DID_INTEL_ARP_S_ESPI_4 0x7f04 +#define PCI_DID_INTEL_ARP_S_ESPI_5 0x7f05 +#define PCI_DID_INTEL_ARP_S_ESPI_6 0x7f06 +#define PCI_DID_INTEL_ARP_S_ESPI_7 0x7f07 +#define PCI_DID_INTEL_ARP_S_ESPI_8 0x7f08 +#define PCI_DID_INTEL_ARP_S_ESPI_9 0x7f09 +#define PCI_DID_INTEL_ARP_S_ESPI_10 0x7f0a +#define PCI_DID_INTEL_ARP_S_ESPI_11 0x7f0b +#define PCI_DID_INTEL_ARP_S_ESPI_12 0x7f0c +#define PCI_DID_INTEL_ARP_S_ESPI_13 0x7f0d +#define PCI_DID_INTEL_ARP_S_ESPI_14 0x7f0e +#define PCI_DID_INTEL_ARP_S_ESPI_15 0x7f0f +#define PCI_DID_INTEL_ARP_S_ESPI_16 0x7f10 +#define PCI_DID_INTEL_ARP_S_ESPI_17 0x7f11 +#define PCI_DID_INTEL_ARP_S_ESPI_18 0x7f12 +#define PCI_DID_INTEL_ARP_S_ESPI_19 0x7f13 +#define PCI_DID_INTEL_ARP_S_ESPI_20 0x7f14 +#define PCI_DID_INTEL_ARP_S_ESPI_21 0x7f15 +#define PCI_DID_INTEL_ARP_S_ESPI_22 0x7f16 +#define PCI_DID_INTEL_ARP_S_ESPI_23 0x7f17 +#define PCI_DID_INTEL_ARP_S_ESPI_24 0x7f18 +#define PCI_DID_INTEL_ARP_S_ESPI_25 0x7f19 +#define PCI_DID_INTEL_ARP_S_ESPI_26 0x7f1a +#define PCI_DID_INTEL_ARP_S_ESPI_27 0x7f1b +#define PCI_DID_INTEL_ARP_S_ESPI_28 0x7f1c +#define PCI_DID_INTEL_ARP_S_ESPI_29 0x7f1d +#define PCI_DID_INTEL_ARP_S_ESPI_30 0x7f1e +#define PCI_DID_INTEL_ARP_S_ESPI_31 0x7f1f #define PCI_DID_INTEL_RPP_P_ESPI_0 0x5180 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182 @@ -3617,6 +3682,34 @@ #define PCI_DID_INTEL_ARL_SOC_PCIE_RP7 0x773e #define PCI_DID_INTEL_ARL_SOC_PCIE_RP8 0x773f #define PCI_DID_INTEL_ARL_SOC_PCIE_RP9 0x774d +#define PCI_DID_INTEL_ARL_S_PCIE_RP13 0xae4d +#define PCI_DID_INTEL_ARL_S_PCIE_RP14 0xae4e +#define PCI_DID_INTEL_ARL_S_PCIE_RP15 0xae4f + +#define PCI_DID_INTEL_ARP_S_PCIE_RP1 0x7f38 +#define PCI_DID_INTEL_ARP_S_PCIE_RP2 0x7f39 +#define PCI_DID_INTEL_ARP_S_PCIE_RP3 0x7f3a +#define PCI_DID_INTEL_ARP_S_PCIE_RP4 0x7f3b +#define PCI_DID_INTEL_ARP_S_PCIE_RP5 0x7f3c +#define PCI_DID_INTEL_ARP_S_PCIE_RP6 0x7f3d +#define PCI_DID_INTEL_ARP_S_PCIE_RP7 0x7f3e +#define PCI_DID_INTEL_ARP_S_PCIE_RP8 0x7f3f +#define PCI_DID_INTEL_ARP_S_PCIE_RP9 0x7f30 +#define PCI_DID_INTEL_ARP_S_PCIE_RP10 0x7f31 +#define PCI_DID_INTEL_ARP_S_PCIE_RP11 0x7f32 +#define PCI_DID_INTEL_ARP_S_PCIE_RP12 0x7f33 +#define PCI_DID_INTEL_ARP_S_PCIE_RP13 0x7f34 +#define PCI_DID_INTEL_ARP_S_PCIE_RP14 0x7f35 +#define PCI_DID_INTEL_ARP_S_PCIE_RP15 0x7f36 +#define PCI_DID_INTEL_ARP_S_PCIE_RP16 0x7f37 +#define PCI_DID_INTEL_ARP_S_PCIE_RP17 0x7f40 +#define PCI_DID_INTEL_ARP_S_PCIE_RP18 0x7f41 +#define PCI_DID_INTEL_ARP_S_PCIE_RP19 0x7f42 +#define PCI_DID_INTEL_ARP_S_PCIE_RP20 0x7f43 +#define PCI_DID_INTEL_ARP_S_PCIE_RP21 0x7f44 +#define PCI_DID_INTEL_ARP_S_PCIE_RP22 0x7f45 +#define PCI_DID_INTEL_ARP_S_PCIE_RP23 0x7f46 +#define PCI_DID_INTEL_ARP_S_PCIE_RP24 0x7f47 #define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d @@ -3779,6 +3872,8 @@ #define PCI_DID_INTEL_ADP_M_SATA_3 0x282a #define PCI_DID_INTEL_MTL_SATA 0x7e63 #define PCI_DID_INTEL_ARL_SATA 0x7763 +#define PCI_DID_INTEL_ARP_S_SATA_1 0x7f62 +#define PCI_DID_INTEL_ARP_S_SATA_2 0x7f66 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 #define PCI_DID_INTEL_RPP_S_SATA 0x7a62 @@ -3809,6 +3904,8 @@ #define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe #define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece #define PCI_DID_INTEL_ARL_SOC_PMC 0x7721 +#define PCI_DID_INTEL_ARL_IOE_S_PMC 0xae21 +#define PCI_DID_INTEL_ARP_S_PMC 0x7f21 #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 @@ -3945,6 +4042,13 @@ #define PCI_DID_INTEL_ARL_I2C4 0x7750 #define PCI_DID_INTEL_ARL_I2C5 0x7751 +#define PCI_DID_INTEL_ARP_S_I2C0 0x7f4c +#define PCI_DID_INTEL_ARP_S_I2C1 0x7f4d +#define PCI_DID_INTEL_ARP_S_I2C2 0x7f4e +#define PCI_DID_INTEL_ARP_S_I2C3 0x7f4f +#define PCI_DID_INTEL_ARP_S_I2C4 0x7f7a +#define PCI_DID_INTEL_ARP_S_I2C5 0x7f7b + #define PCI_DID_INTEL_LNL_I2C0 0xa878 #define PCI_DID_INTEL_LNL_I2C1 0xa879 #define PCI_DID_INTEL_LNL_I2C2 0xa87a @@ -4048,6 +4152,11 @@ #define PCI_DID_INTEL_ARL_UART1 0x7726 #define PCI_DID_INTEL_ARL_UART2 0x7752 +#define PCI_DID_INTEL_ARP_S_UART0 0x7f28 +#define PCI_DID_INTEL_ARP_S_UART1 0x7f29 +#define PCI_DID_INTEL_ARP_S_UART2 0x7f5c +#define PCI_DID_INTEL_ARP_S_UART3 0x7f5d + #define PCI_DID_INTEL_LNL_UART0 0xa825 #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 @@ -4158,6 +4267,13 @@ #define PCI_DID_INTEL_ARL_GSPI1 0x7730 #define PCI_DID_INTEL_ARL_GSPI2 0x7746 +#define PCI_DID_INTEL_ARL_S_HWSEQ_SPI 0xae23 +#define PCI_DID_INTEL_ARP_S_HWSEQ_SPI 0x7f24 +#define PCI_DID_INTEL_ARP_S_GSPI0 0x7f2a +#define PCI_DID_INTEL_ARP_S_GSPI1 0x7f2b +#define PCI_DID_INTEL_ARP_S_GSPI2 0x7f5e +#define PCI_DID_INTEL_ARP_S_GSPI3 0x7f5f + #define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823 #define PCI_DID_INTEL_LNL_GSPI0 0xa827 #define PCI_DID_INTEL_LNL_GSPI1 0xa830 @@ -4318,6 +4434,7 @@ #define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 #define PCI_DID_INTEL_ARL_H_GT2_1 0x7d51 #define PCI_DID_INTEL_ARL_H_GT2_2 0x7dd1 +#define PCI_DID_INTEL_ARL_HX_GT2 0x7d67 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 @@ -4469,6 +4586,9 @@ #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 #define PCI_DID_INTEL_ARL_H_ID_1 0x7d06 #define PCI_DID_INTEL_ARL_H_ID_2 0x7d20 +#define PCI_DID_INTEL_ARL_HX_ID_1 0x7d1c +#define PCI_DID_INTEL_ARL_HX_ID_2 0x7d2d +#define PCI_DID_INTEL_ARL_HX_ID_3 0x7d2f #define PCI_DID_INTEL_RPL_HX_ID_1 0xa702 #define PCI_DID_INTEL_RPL_HX_ID_2 0xa729 #define PCI_DID_INTEL_RPL_HX_ID_3 0xa728 @@ -4525,6 +4645,8 @@ #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22 #define PCI_DID_INTEL_ARL_SMBUS 0x7722 +#define PCI_DID_INTEL_ARL_S_SMBUS 0xae22 +#define PCI_DID_INTEL_ARP_S_SMBUS 0x7f22 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 @@ -4569,6 +4691,7 @@ #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 #define PCI_DID_INTEL_ARL_XHCI 0x777d +#define PCI_DID_INTEL_ARP_S_XHCI 0x7f6e #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d @@ -4603,6 +4726,8 @@ #define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 #define PCI_DID_INTEL_ARL_SOC_P2SB 0x7720 +#define PCI_DID_INTEL_ARL_IOE_S_P2SB 0xae20 +#define PCI_DID_INTEL_ARP_S_P2SB 0x7f20 #define PCI_DID_INTEL_RPP_P_P2SB 0x51a0 #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 @@ -4627,6 +4752,8 @@ #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf #define PCI_DID_INTEL_ARL_SOC_SRAM 0x777f +#define PCI_DID_INTEL_ARL_SOC_S_SRAM 0xae7f +#define PCI_DID_INTEL_ARP_S_SRAM 0x7f27 #define PCI_DID_INTEL_LNL_SRAM 0xa87f #define PCI_DID_INTEL_PTL_H_SRAM 0xe47f #define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f @@ -4689,6 +4816,8 @@ #define PCI_DID_INTEL_ARL_AUDIO 0x7728 +#define PCI_DID_INTEL_ARP_S_AUDIO 0x7f50 + #define PCI_DID_INTEL_LNL_AUDIO_1 0xa828 #define PCI_DID_INTEL_LNL_AUDIO_2 0xa829 #define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a @@ -4760,6 +4889,13 @@ #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_ARL_CSE0 0x7770 +#define PCI_DID_INTEL_ARL_S_CSE0 0xae70 +#define PCI_DID_INTEL_ARL_S_CSE1 0xae71 +#define PCI_DID_INTEL_ARL_S_CSE2 0xae74 +#define PCI_DID_INTEL_ARP_S_CSE0 0x7f68 +#define PCI_DID_INTEL_ARP_S_CSE1 0x7f69 +#define PCI_DID_INTEL_ARP_S_CSE2 0x7f6c +#define PCI_DID_INTEL_ARP_S_CSE3 0x7f6d #define PCI_DID_INTEL_LNL_CSE0 0xa870 #define PCI_DID_INTEL_PTL_H_CSE0 0xe470 #define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370 @@ -4788,6 +4924,7 @@ #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 #define PCI_DID_INTEL_ARL_XDCI 0x777e +#define PCI_DID_INTEL_ARP_S_XDCI 0x7f6f #define PCI_DID_INTEL_PTL_H_XDCI 0xe47e #define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e @@ -4899,6 +5036,7 @@ #define PCI_DID_INTEL_JSL_DTT 0x4E03 #define PCI_DID_INTEL_ADL_DTT 0x461d #define PCI_DID_INTEL_MTL_DTT 0x7d03 +#define PCI_DID_INTEL_ARL_S_DTT 0xad03 #define PCI_DID_INTEL_RPL_DTT 0xa71d #define PCI_DID_INTEL_PTL_DTT 0xb01d @@ -4944,6 +5082,7 @@ #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 #define PCI_DID_INTEL_ARL_CNVI_WIFI 0x7740 +#define PCI_DID_INTEL_ARP_S_CNVI_WIFI 0x7f70 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 @@ -4980,6 +5119,7 @@ #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM 0x54ef #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM 0xa0ef #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d +#define PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM 0xad0d #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM 0x7a27 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM 0xb07d @@ -4987,6 +5127,8 @@ /* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 #define PCI_DID_INTEL_ARL_TRACEHUB 0x7724 +#define PCI_DID_INTEL_ARL_S_TRACEHUB 0xae24 +#define PCI_DID_INTEL_ARP_S_TRACEHUB 0x7f26 #define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f #define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324 @@ -5013,6 +5155,10 @@ #define PCI_DID_INTEL_ARL_THC0_2 0x7749 #define PCI_DID_INTEL_ARL_THC1_1 0x774a #define PCI_DID_INTEL_ARL_THC1_2 0x774b +#define PCI_DID_INTEL_ARP_S_THC0_1 0x7f58 +#define PCI_DID_INTEL_ARP_S_THC0_2 0x7f59 +#define PCI_DID_INTEL_ARP_S_THC1_1 0x7f5a +#define PCI_DID_INTEL_ARP_S_THC1_2 0x7f5b #define PCI_VID_COMPUTONE 0x8e0e #define PCI_DID_COMPUTONE_IP2EX 0x0291 diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig index d55c8ef86a..6cb7c0ee4d 100644 --- a/src/mainboard/system76/mtl/Kconfig +++ b/src/mainboard/system76/mtl/Kconfig @@ -25,6 +25,16 @@ config BOARD_SYSTEM76_MTL_COMMON select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config BOARD_SYSTEM76_BONW16 + select BOARD_SYSTEM76_MTL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + select DRIVERS_INTEL_DTBT + select EC_SYSTEM76_EC_DGPU + select PCIEXP_HOTPLUG + select SOC_INTEL_METEORLAKE_U_H # TODO: Arrow Lake-HX + select SOC_INTEL_ARROWLAKE_PCH_S + config BOARD_SYSTEM76_DARP10 select BOARD_SYSTEM76_MTL_COMMON select EC_SYSTEM76_EC_FAN2 @@ -73,6 +83,7 @@ config MAINBOARD_DIR default "system76/mtl" config VARIANT_DIR + default "bonw16" if BOARD_SYSTEM76_BONW16 default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B default "darp11" if BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B @@ -81,6 +92,7 @@ config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER + default "bonw16" if BOARD_SYSTEM76_BONW16 default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10-b" if BOARD_SYSTEM76_DARP10_B default "darp11" if BOARD_SYSTEM76_DARP11 @@ -89,10 +101,12 @@ config MAINBOARD_PART_NUMBER default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Bonobo WS" if BOARD_SYSTEM76_BONW16 default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B || BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B config MAINBOARD_VERSION + default "bonw16" if BOARD_SYSTEM76_BONW16 default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10-b" if BOARD_SYSTEM76_DARP10_B default "darp11" if BOARD_SYSTEM76_DARP11 diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name index b0e214e866..a149835710 100644 --- a/src/mainboard/system76/mtl/Kconfig.name +++ b/src/mainboard/system76/mtl/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_SYSTEM76_BONW16 + bool "bonw16" + config BOARD_SYSTEM76_DARP10 bool "darp10" diff --git a/src/mainboard/system76/mtl/variants/bonw16/board.fmd b/src/mainboard/system76/mtl/variants/bonw16/board.fmd new file mode 100644 index 0000000000..0e3414bf24 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 16K + SI_ME 10472K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/mtl/variants/bonw16/board_info.txt b/src/mainboard/system76/mtl/variants/bonw16/board_info.txt new file mode 100644 index 0000000000..563fb41418 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/board_info.txt @@ -0,0 +1,2 @@ +Board name: bonw16 +Release year: 2025 diff --git a/src/mainboard/system76/mtl/variants/bonw16/data.vbt b/src/mainboard/system76/mtl/variants/bonw16/data.vbt new file mode 100644 index 0000000000..835d8b3498 Binary files /dev/null and b/src/mainboard/system76/mtl/variants/bonw16/data.vbt differ diff --git a/src/mainboard/system76/mtl/variants/bonw16/gpio.c b/src/mainboard/system76/mtl/variants/bonw16/gpio.c new file mode 100644 index 0000000000..e8930f2c89 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/gpio.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { +//TODO +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/bonw16/gpio_early.c b/src/mainboard/system76/mtl/variants/bonw16/gpio_early.c new file mode 100644 index 0000000000..3533dd8403 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/gpio_early.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { +//TODO +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/bonw16/hda_verb.c b/src/mainboard/system76/mtl/variants/bonw16/hda_verb.c new file mode 100644 index 0000000000..3bf991b84b --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x15585802, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15585802), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60120), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x41a7932d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/bonw16/overridetree.cb b/src/mainboard/system76/mtl/variants/bonw16/overridetree.cb new file mode 100644 index 0000000000..cb690b2905 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/overridetree.cb @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/meteorlake + device domain 0 on + subsystemid 0x1558 0x5802 inherit + + #TODO + end +end \ No newline at end of file diff --git a/src/mainboard/system76/mtl/variants/bonw16/ramstage.c b/src/mainboard/system76/mtl/variants/bonw16/ramstage.c new file mode 100644 index 0000000000..3402756ea1 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/ramstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + //TODO: TCP USB-A conversion? + + // XXX: Enabling C10 reporting causes system to constantly enter and + // exit opportunistic suspend when idle. + params->PchEspiHostC10ReportEnable = 0; +} diff --git a/src/mainboard/system76/mtl/variants/bonw16/romstage.c b/src/mainboard/system76/mtl/variants/bonw16/romstage.c new file mode 100644 index 0000000000..4c35d9149d --- /dev/null +++ b/src/mainboard/system76/mtl/variants/bonw16/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51 + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index d939738e48..3e562afa36 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -458,6 +458,7 @@ static const unsigned short wifi_pci_device_ids[] = { PCI_DID_INTEL_MTL_CNVI_WIFI_2, PCI_DID_INTEL_MTL_CNVI_WIFI_3, PCI_DID_INTEL_ARL_CNVI_WIFI, + PCI_DID_INTEL_ARP_S_CNVI_WIFI, PCI_DID_INTEL_CML_LP_CNVI_WIFI, PCI_DID_INTEL_CML_H_CNVI_WIFI, PCI_DID_INTEL_CNL_LP_CNVI_WIFI, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 3fd5232167..ea6552c18a 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -40,6 +40,8 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_S_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_S_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 243b5af0f9..810c3a7191 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1522,6 +1522,13 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, PCI_DID_INTEL_ARL_CSE0, + PCI_DID_INTEL_ARL_S_CSE0, + PCI_DID_INTEL_ARL_S_CSE1, + PCI_DID_INTEL_ARL_S_CSE2, + PCI_DID_INTEL_ARP_S_CSE0, + PCI_DID_INTEL_ARP_S_CSE1, + PCI_DID_INTEL_ARP_S_CSE2, + PCI_DID_INTEL_ARP_S_CSE3, PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_GLK_CSE0, PCI_DID_INTEL_CNL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 59593bc0c4..ad258c5d4e 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -46,6 +46,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, PCI_DID_INTEL_ARL_AUDIO, + PCI_DID_INTEL_ARP_S_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index 8b086e0fb9..f2c7581262 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -11,6 +11,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_DTT, PCI_DID_INTEL_RPL_DTT, PCI_DID_INTEL_MTL_DTT, + PCI_DID_INTEL_ARL_S_DTT, PCI_DID_INTEL_CML_DTT, PCI_DID_INTEL_TGL_DTT, PCI_DID_INTEL_JSL_DTT, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index b5ee53a715..f7abaa2743 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -578,6 +578,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MTL_HWSEQ_SPI, PCI_DID_INTEL_ARL_HWSEQ_SPI, + PCI_DID_INTEL_ARL_S_HWSEQ_SPI, + PCI_DID_INTEL_ARP_S_HWSEQ_SPI, PCI_DID_INTEL_RPP_S_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_TGP_SPI0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ad4c4cec27..63a1f3ce0e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -365,6 +365,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_P_GT2_5, PCI_DID_INTEL_ARL_H_GT2_1, PCI_DID_INTEL_ARL_H_GT2_2, + PCI_DID_INTEL_ARL_HX_GT2, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 7af1b251ad..a69805e0e4 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, PCI_DID_INTEL_ARL_AUDIO, + PCI_DID_INTEL_ARP_S_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index a4e6aae615..db6b84b5d5 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -204,6 +204,12 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ARL_I2C3, PCI_DID_INTEL_ARL_I2C4, PCI_DID_INTEL_ARL_I2C5, + PCI_DID_INTEL_ARP_S_I2C0, + PCI_DID_INTEL_ARP_S_I2C1, + PCI_DID_INTEL_ARP_S_I2C2, + PCI_DID_INTEL_ARP_S_I2C3, + PCI_DID_INTEL_ARP_S_I2C4, + PCI_DID_INTEL_ARP_S_I2C5, PCI_DID_INTEL_APL_I2C0, PCI_DID_INTEL_APL_I2C1, PCI_DID_INTEL_APL_I2C2, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 09b6ab9b15..b46fc95294 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -234,6 +234,70 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ARL_H_ESPI_0, PCI_DID_INTEL_ARL_H_ESPI_1, PCI_DID_INTEL_ARL_U_ESPI_0, + PCI_DID_INTEL_ARL_S_ESPI_0, + PCI_DID_INTEL_ARL_S_ESPI_1, + PCI_DID_INTEL_ARL_S_ESPI_2, + PCI_DID_INTEL_ARL_S_ESPI_3, + PCI_DID_INTEL_ARL_S_ESPI_4, + PCI_DID_INTEL_ARL_S_ESPI_5, + PCI_DID_INTEL_ARL_S_ESPI_6, + PCI_DID_INTEL_ARL_S_ESPI_7, + PCI_DID_INTEL_ARL_S_ESPI_8, + PCI_DID_INTEL_ARL_S_ESPI_9, + PCI_DID_INTEL_ARL_S_ESPI_10, + PCI_DID_INTEL_ARL_S_ESPI_11, + PCI_DID_INTEL_ARL_S_ESPI_12, + PCI_DID_INTEL_ARL_S_ESPI_13, + PCI_DID_INTEL_ARL_S_ESPI_14, + PCI_DID_INTEL_ARL_S_ESPI_15, + PCI_DID_INTEL_ARL_S_ESPI_16, + PCI_DID_INTEL_ARL_S_ESPI_17, + PCI_DID_INTEL_ARL_S_ESPI_18, + PCI_DID_INTEL_ARL_S_ESPI_19, + PCI_DID_INTEL_ARL_S_ESPI_20, + PCI_DID_INTEL_ARL_S_ESPI_21, + PCI_DID_INTEL_ARL_S_ESPI_22, + PCI_DID_INTEL_ARL_S_ESPI_23, + PCI_DID_INTEL_ARL_S_ESPI_24, + PCI_DID_INTEL_ARL_S_ESPI_25, + PCI_DID_INTEL_ARL_S_ESPI_26, + PCI_DID_INTEL_ARL_S_ESPI_27, + PCI_DID_INTEL_ARL_S_ESPI_28, + PCI_DID_INTEL_ARL_S_ESPI_29, + PCI_DID_INTEL_ARL_S_ESPI_30, + PCI_DID_INTEL_ARL_S_ESPI_31, + PCI_DID_INTEL_ARP_S_ESPI_0, + PCI_DID_INTEL_ARP_S_ESPI_1, + PCI_DID_INTEL_ARP_S_ESPI_2, + PCI_DID_INTEL_ARP_S_ESPI_3, + PCI_DID_INTEL_ARP_S_ESPI_4, + PCI_DID_INTEL_ARP_S_ESPI_5, + PCI_DID_INTEL_ARP_S_ESPI_6, + PCI_DID_INTEL_ARP_S_ESPI_7, + PCI_DID_INTEL_ARP_S_ESPI_8, + PCI_DID_INTEL_ARP_S_ESPI_9, + PCI_DID_INTEL_ARP_S_ESPI_10, + PCI_DID_INTEL_ARP_S_ESPI_11, + PCI_DID_INTEL_ARP_S_ESPI_12, + PCI_DID_INTEL_ARP_S_ESPI_13, + PCI_DID_INTEL_ARP_S_ESPI_14, + PCI_DID_INTEL_ARP_S_ESPI_15, + PCI_DID_INTEL_ARP_S_ESPI_16, + PCI_DID_INTEL_ARP_S_ESPI_17, + PCI_DID_INTEL_ARP_S_ESPI_18, + PCI_DID_INTEL_ARP_S_ESPI_19, + PCI_DID_INTEL_ARP_S_ESPI_20, + PCI_DID_INTEL_ARP_S_ESPI_21, + PCI_DID_INTEL_ARP_S_ESPI_22, + PCI_DID_INTEL_ARP_S_ESPI_23, + PCI_DID_INTEL_ARP_S_ESPI_24, + PCI_DID_INTEL_ARP_S_ESPI_25, + PCI_DID_INTEL_ARP_S_ESPI_26, + PCI_DID_INTEL_ARP_S_ESPI_27, + PCI_DID_INTEL_ARP_S_ESPI_28, + PCI_DID_INTEL_ARP_S_ESPI_29, + PCI_DID_INTEL_ARP_S_ESPI_30, + PCI_DID_INTEL_ARP_S_ESPI_31, PCI_DID_INTEL_RPP_P_ESPI_0, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 2bc3c70da5..9b8b386b02 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -142,6 +142,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, PCI_DID_INTEL_ARL_SOC_P2SB, + PCI_DID_INTEL_ARL_IOE_S_P2SB, + PCI_DID_INTEL_ARP_S_P2SB, PCI_DID_INTEL_RPP_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 677d2577af..d34dab10ce 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -121,6 +121,33 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_ARL_SOC_PCIE_RP7, PCI_DID_INTEL_ARL_SOC_PCIE_RP8, PCI_DID_INTEL_ARL_SOC_PCIE_RP9, + PCI_DID_INTEL_ARL_S_PCIE_RP13, + PCI_DID_INTEL_ARL_S_PCIE_RP14, + PCI_DID_INTEL_ARL_S_PCIE_RP15, + PCI_DID_INTEL_ARP_S_PCIE_RP1, + PCI_DID_INTEL_ARP_S_PCIE_RP2, + PCI_DID_INTEL_ARP_S_PCIE_RP3, + PCI_DID_INTEL_ARP_S_PCIE_RP4, + PCI_DID_INTEL_ARP_S_PCIE_RP5, + PCI_DID_INTEL_ARP_S_PCIE_RP6, + PCI_DID_INTEL_ARP_S_PCIE_RP7, + PCI_DID_INTEL_ARP_S_PCIE_RP8, + PCI_DID_INTEL_ARP_S_PCIE_RP9, + PCI_DID_INTEL_ARP_S_PCIE_RP10, + PCI_DID_INTEL_ARP_S_PCIE_RP11, + PCI_DID_INTEL_ARP_S_PCIE_RP12, + PCI_DID_INTEL_ARP_S_PCIE_RP13, + PCI_DID_INTEL_ARP_S_PCIE_RP14, + PCI_DID_INTEL_ARP_S_PCIE_RP15, + PCI_DID_INTEL_ARP_S_PCIE_RP16, + PCI_DID_INTEL_ARP_S_PCIE_RP17, + PCI_DID_INTEL_ARP_S_PCIE_RP18, + PCI_DID_INTEL_ARP_S_PCIE_RP19, + PCI_DID_INTEL_ARP_S_PCIE_RP20, + PCI_DID_INTEL_ARP_S_PCIE_RP21, + PCI_DID_INTEL_ARP_S_PCIE_RP22, + PCI_DID_INTEL_ARP_S_PCIE_RP23, + PCI_DID_INTEL_ARP_S_PCIE_RP24, PCI_DID_INTEL_LWB_PCIE_RP1, PCI_DID_INTEL_LWB_PCIE_RP2, PCI_DID_INTEL_LWB_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 57b00c1c60..0f20752991 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -118,6 +118,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_IOE_M_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC, PCI_DID_INTEL_ARL_SOC_PMC, + PCI_DID_INTEL_ARL_IOE_S_PMC, + PCI_DID_INTEL_ARP_S_PMC, PCI_DID_INTEL_RPP_P_PMC, PCI_DID_INTEL_DNV_PMC, PCI_DID_INTEL_LWB_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index ae51efa95c..f406096c85 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -37,6 +37,8 @@ struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SATA, PCI_DID_INTEL_ARL_SATA, + PCI_DID_INTEL_ARP_S_SATA_1, + PCI_DID_INTEL_ARP_S_SATA_2, PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_S_SATA, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 62a44b470d..346b43fc63 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -54,6 +54,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_ARL_SMBUS, + PCI_DID_INTEL_ARL_S_SMBUS, + PCI_DID_INTEL_ARP_S_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_S_SMBUS, PCI_DID_INTEL_APL_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index beac292c41..e59a12a0a3 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -140,6 +140,10 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ARL_GSPI0, PCI_DID_INTEL_ARL_GSPI1, PCI_DID_INTEL_ARL_GSPI2, + PCI_DID_INTEL_ARP_S_GSPI0, + PCI_DID_INTEL_ARP_S_GSPI1, + PCI_DID_INTEL_ARP_S_GSPI2, + PCI_DID_INTEL_ARP_S_GSPI3, PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 62cfab539c..3bfe003940 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -41,7 +41,10 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_IOE_M_SRAM, PCI_DID_INTEL_MTL_IOE_P_SRAM, PCI_DID_INTEL_MTL_CRASHLOG_SRAM, + PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM, PCI_DID_INTEL_ARL_SOC_SRAM, + PCI_DID_INTEL_ARL_SOC_S_SRAM, + PCI_DID_INTEL_ARP_S_SRAM, PCI_DID_INTEL_APL_SRAM, PCI_DID_INTEL_GLK_SRAM, PCI_DID_INTEL_CMP_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index f91dd98305..aa8fc8a9d5 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -440,6 +440,9 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_MTL_P_ID_5, PCI_DID_INTEL_ARL_H_ID_1, PCI_DID_INTEL_ARL_H_ID_2, + PCI_DID_INTEL_ARL_HX_ID_1, + PCI_DID_INTEL_ARL_HX_ID_2, + PCI_DID_INTEL_ARL_HX_ID_3, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c index c9f4228109..641b6f9987 100644 --- a/src/soc/intel/common/block/tracehub/tracehub.c +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -46,6 +46,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_TRACEHUB, PCI_DID_INTEL_MTL_TRACEHUB, PCI_DID_INTEL_ARL_TRACEHUB, + PCI_DID_INTEL_ARL_S_TRACEHUB, + PCI_DID_INTEL_ARP_S_TRACEHUB, PCI_DID_INTEL_RPL_TRACEHUB, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index e42db4257a..13dba3f5ca 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -372,6 +372,10 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ARL_UART0, PCI_DID_INTEL_ARL_UART1, PCI_DID_INTEL_ARL_UART2, + PCI_DID_INTEL_ARP_S_UART0, + PCI_DID_INTEL_ARP_S_UART1, + PCI_DID_INTEL_ARP_S_UART2, + PCI_DID_INTEL_ARP_S_UART3, PCI_DID_INTEL_APL_UART0, PCI_DID_INTEL_APL_UART1, PCI_DID_INTEL_APL_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index bd3917cae6..e2404c795f 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -32,6 +32,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_XDCI, PCI_DID_INTEL_MTL_XDCI, PCI_DID_INTEL_ARL_XDCI, + PCI_DID_INTEL_ARP_S_XDCI, PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_CNL_LP_XDCI, PCI_DID_INTEL_GLK_XDCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 1cdf21f45c..33c4e7ea64 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -136,6 +136,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, PCI_DID_INTEL_ARL_XHCI, + PCI_DID_INTEL_ARP_S_XHCI, PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_CNL_LP_XHCI, PCI_DID_INTEL_GLK_XHCI, diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index c59d456285..4cd0d61dd2 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -69,7 +69,7 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC - select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ARROWLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_IOE_P2SB select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 @@ -136,6 +136,11 @@ config SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON silicon. Typically known as engineering samples (like ES). This type of the silicon are very common for early platform development. +config SOC_INTEL_ARROWLAKE_PCH_S + bool + help + Choose this option if your mainboard has an Arrow Lake PCH-S chipset. + if SOC_INTEL_METEORLAKE config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT @@ -157,7 +162,7 @@ config METEORLAKE_CAR_ENHANCED_NEM config MAX_CPUS int - default 22 + default 24 config DCACHE_RAM_BASE default 0xfef00000 @@ -187,6 +192,7 @@ config FSP_TEMP_RAM_SIZE config CHIPSET_DEVICETREE string + default "soc/intel/meteorlake/chipset_pch_s.cb" if SOC_INTEL_ARROWLAKE_PCH_S default "soc/intel/meteorlake/chipset.cb" config EXT_BIOS_WIN_BASE @@ -225,14 +231,17 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config MAX_TBT_ROOT_PORTS int + default 2 if SOC_INTEL_ARROWLAKE_PCH_S default 4 config MAX_ROOT_PORTS int + default 24 if SOC_INTEL_ARROWLAKE_PCH_S default 12 config MAX_PCIE_CLOCK_SRC int + default 14 if SOC_INTEL_ARROWLAKE_PCH_S default 9 config SMM_TSEG_SIZE diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index f3dce87131..5c6d9161bf 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -57,6 +57,15 @@ smm-y += smihandler.c smm-y += soc_info.c smm-y += uart.c smm-y += xhci.c + +ifeq ($(CONFIG_SOC_INTEL_ARROWLAKE_PCH_S),y) +all-y += gpio_pch_s.c +smm-y += gpio_pch_s.c +else +all-y += gpio.c +smm-y += gpio.c +endif + CPPFLAGS_common += -I$(src)/soc/intel/meteorlake CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 4744abb2c7..5d8ee694ba 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -23,6 +23,8 @@ static struct { { CPUID_METEORLAKE_B0, "MeteorLake B0" }, { CPUID_METEORLAKE_C0, "MeteorLake C0" }, { CPUID_ARROWLAKE_H_A0, "ArrowLake-H A0" }, + { CPUID_ARROWLAKE_S_A0, "ArrowLake-S A0" }, + { CPUID_ARROWLAKE_S_B0, "ArrowLake-S B0" }, }; static struct { @@ -37,6 +39,9 @@ static struct { { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, { PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" }, { PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" }, + { PCI_DID_INTEL_ARL_HX_ID_1, "ArrowLake-HX (8+16)" }, + { PCI_DID_INTEL_ARL_HX_ID_2, "ArrowLake-HX (8+12)" }, + { PCI_DID_INTEL_ARL_HX_ID_3, "ArrowLake-HX (6+8)" }, }; static struct { @@ -54,6 +59,38 @@ static struct { { PCI_DID_INTEL_ARL_H_ESPI_0, "ArrowLake-H SOC" }, { PCI_DID_INTEL_ARL_H_ESPI_1, "ArrowLake-H SOC" }, { PCI_DID_INTEL_ARL_U_ESPI_0, "ArrowLake-U SOC" }, + { PCI_DID_INTEL_ARP_S_ESPI_0, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_1, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_2, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_3, "ArrowLake-S Q870" }, + { PCI_DID_INTEL_ARP_S_ESPI_4, "ArrowLake-S Z890" }, + { PCI_DID_INTEL_ARP_S_ESPI_5, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_6, "ArrowLake-S B860" }, + { PCI_DID_INTEL_ARP_S_ESPI_7, "ArrowLake-S H810" }, + { PCI_DID_INTEL_ARP_S_ESPI_8, "ArrowLake-S W880" }, + { PCI_DID_INTEL_ARP_S_ESPI_9, "ArrowLake-S W890" }, + { PCI_DID_INTEL_ARP_S_ESPI_10, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_11, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_12, "ArrowLake-S HM870" }, + { PCI_DID_INTEL_ARP_S_ESPI_13, "ArrowLake-S WM880" }, + { PCI_DID_INTEL_ARP_S_ESPI_14, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_15, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_16, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_17, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_18, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_19, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_20, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_21, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_22, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_23, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_24, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_25, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_26, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_27, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_28, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_29, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_30, "ArrowLake-S PCH" }, + { PCI_DID_INTEL_ARP_S_ESPI_31, "ArrowLake-S PCH" }, }; static struct { @@ -68,6 +105,7 @@ static struct { { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, { PCI_DID_INTEL_ARL_H_GT2_1, "ArrowLake-H GT2" }, { PCI_DID_INTEL_ARL_H_GT2_2, "ArrowLake-H GT2" }, + { PCI_DID_INTEL_ARL_HX_GT2, "ArrowLake-HX GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 4ef8fd5184..7b647e3d8d 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -46,13 +46,17 @@ struct ibecc_config { enum soc_intel_meteorlake_power_limits { MTL_P_282_242_CORE, MTL_P_682_482_CORE, + ARL_HX_8_16_55W_CORE, + ARL_HX_8_12_55W_CORE, + ARL_HX_6_8_55W_CORE, MTL_POWER_LIMITS_COUNT }; /* TDP values for different SKUs */ enum soc_intel_meteorlake_cpu_tdps { TDP_15W = 15, - TDP_28W = 28 + TDP_28W = 28, + TDP_55W = 55 }; /* Mapping of different SKUs based on CPU ID and TDP values */ @@ -67,6 +71,9 @@ static const struct { { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_HX_ID_1, ARL_HX_8_16_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_ARL_HX_ID_2, ARL_HX_8_12_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_ARL_HX_ID_3, ARL_HX_6_8_55W_CORE, TDP_55W }, }; /* Types of display ports */ diff --git a/src/soc/intel/meteorlake/chipset_pch_s.cb b/src/soc/intel/meteorlake/chipset_pch_s.cb new file mode 100644 index 0000000000..c83a0e39e6 --- /dev/null +++ b/src/soc/intel/meteorlake/chipset_pch_s.cb @@ -0,0 +1,229 @@ +chip soc/intel/meteorlake + + device cpu_cluster 0 on end + + register "power_limits_config[ARL_HX_8_16_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 160, + .tdp_pl4 = 266, + }" + + register "power_limits_config[ARL_HX_8_12_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 144, + .tdp_pl4 = 257, + }" + + register "power_limits_config[ARL_HX_6_8_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 108, + .tdp_pl4 = 204, + }" + + # Reduce the size of BasicMemoryTests to speed up the boot time. + register "lower_basic_mem_test_size" = "true" + + # The power state current threshold is defined in 1/4 A + # increments. A value of 400 = 100A. + register "ps_cur_2_threshold[VR_DOMAIN_SA]" = "40" # 10A + + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + register "common_soc_config.pch_thermal_trip" = "130" + + # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) + register "tcc_offset" = "20" + + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 01.0 alias pcie_rp12 off end + device pci 02.0 alias igpu off end + device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end + device pci 06.0 alias pcie_rp13 off end + device pci 06.1 alias pcie_rp10 off end + device pci 06.3 alias pcie_rp14 off end + device pci 06.4 alias pcie_rp15 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 08.0 alias gna off end + device pci 0a.0 alias crashlog on end + device pci 0b.0 alias vpu off end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port0 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port1 off end + end + end + end + end + device pci 0d.1 alias tcss_xdci off end + device pci 0d.2 alias tcss_dma0 off end + device pci 0e.0 alias vmd off end + device pci 10.0 alias thc0 off end + device pci 10.1 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + #TODO: conflict between gspi3 and ioe_p2sb + #TODO device pci 13.0 alias gspi3 off end + device pci 13.0 alias ioe_p2sb hidden end + device pci 13.1 alias uart3 off end + device pci 13.2 alias pmc2 hidden end + device pci 13.3 alias ioe_shared_sram off end + #TODO: conflict between soc_s_shared_sram and xhci! + #TODO device pci 14.0 alias soc_s_shared_sram off end + device pci 14.0 alias xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 2.a alias usb2_port11 off end + end + chip drivers/usb/acpi + device usb 2.b alias usb2_port12 off end + end + chip drivers/usb/acpi + device usb 2.c alias usb2_port13 off end + end + chip drivers/usb/acpi + device usb 2.d alias usb2_port14 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + chip drivers/usb/acpi + device usb 3.4 alias usb3_port5 off end + end + chip drivers/usb/acpi + device usb 3.5 alias usb3_port6 off end + end + chip drivers/usb/acpi + device usb 3.6 alias usb3_port7 off end + end + chip drivers/usb/acpi + device usb 3.7 alias usb3_port8 off end + end + chip drivers/usb/acpi + device usb 3.8 alias usb3_port9 off end + end + chip drivers/usb/acpi + device usb 3.9 alias usb3_port10 off end + end + end + end + end + device pci 14.1 alias usb_otg off end + device pci 14.2 alias pmc_shared_sram off end + device pci 14.3 alias cnvi_wifi off end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 15.4 alias i3c off end + device pci 16.0 alias heci1 on end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 18.0 alias eheci1 off end + device pci 18.1 alias eheci2 off end + device pci 18.2 alias eheci3 off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1b.0 alias pcie_rp17 off end + device pci 1b.1 alias pcie_rp18 off end + device pci 1b.2 alias pcie_rp19 off end + device pci 1b.3 alias pcie_rp20 off end + device pci 1b.4 alias pcie_rp21 off end + device pci 1b.5 alias pcie_rp22 off end + device pci 1b.6 alias pcie_rp23 off end + device pci 1b.7 alias pcie_rp24 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1d.4 alias pcie_rp13 off end + device pci 1d.5 alias pcie_rp14 off end + device pci 1d.6 alias pcie_rp15 off end + device pci 1d.7 alias pcie_rp16 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias soc_espi on end + device pci 1f.1 alias p2sb hidden end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias npk off end + end +end diff --git a/src/soc/intel/meteorlake/include/soc/gpio.h b/src/soc/intel/meteorlake/include/soc/gpio.h index 50a33a585e..3cd5c3a73c 100644 --- a/src/soc/intel/meteorlake/include/soc/gpio.h +++ b/src/soc/intel/meteorlake/include/soc/gpio.h @@ -3,11 +3,17 @@ #ifndef _SOC_METEORLAKE_GPIO_H_ #define _SOC_METEORLAKE_GPIO_H_ +#if CONFIG(SOC_INTEL_ARROWLAKE_PCH_S) +#include +#define CROS_GPIO_NAME "INTC1084" +#define CROS_GPIO_DEVICE_NAME "INTC1084:00" +#else #include -#include - #define CROS_GPIO_NAME "INTC1083" #define CROS_GPIO_DEVICE_NAME "INTC1083:00" +#endif + +#include /* Enable GPIO community power management configuration */ #define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \