🐛 accgen fixes (#252)

-fix problem with templates after linting
-make templates comply with new accelerator inference
-miscellaneous cleanup

Author: jzuckerman

accelerators/stratus_hls/test_stratus/hw/hls/Makefile

@@ -0,0 +1 @@
+../../../common/hls/Makefile

accelerators/stratus_hls/test_stratus/hw/hls/project.tcl

@@ -0,0 +1,105 @@
+# Copyright (c) 2011-2024 Columbia University, System Level Design Group
+# SPDX-License-Identifier: Apache-2.0
+
+############################################################
+# Design Parameters
+############################################################
+
+#
+# Source the common configurations
+#
+source ../../../common/hls/project.tcl
+
+
+#
+# Set the private memory library
+#
+use_hls_lib "./memlib"
+
+
+#
+# Local synthesis attributes
+#
+if {$TECH eq "virtex7"} {
+    # Library is in ns, but simulation uses ps!
+    set CLOCK_PERIOD 10.0
+    set SIM_CLOCK_PERIOD 10000.0
+    set_attr default_input_delay      0.1
+}
+if {$TECH eq "zynq7000"} {
+    # Library is in ns, but simulation uses ps!
+    set CLOCK_PERIOD 10.0
+    set SIM_CLOCK_PERIOD 10000.0
+    set_attr default_input_delay      0.1
+}
+if {$TECH eq "virtexu"} {
+    # Library is in ns, but simulation uses ps!
+    set CLOCK_PERIOD 8.0
+    set SIM_CLOCK_PERIOD 8000.0
+    set_attr default_input_delay      0.1
+}
+if {$TECH eq "virtexup"} {
+    # Library is in ns, but simulation uses ps!
+    set CLOCK_PERIOD 6.4
+    set SIM_CLOCK_PERIOD 6400.0
+    set_attr default_input_delay      0.1
+}
+if {$TECH eq "cmos32soi"} {
+    set CLOCK_PERIOD 1000.0
+    set SIM_CLOCK_PERIOD 1000.0
+    set_attr default_input_delay      100.0
+}
+if {$TECH eq "gf12"} {
+    set CLOCK_PERIOD 1.0
+    set SIM_CLOCK_PERIOD 1.0
+    set_attr default_input_delay      0.1
+}
+set_attr clock_period $CLOCK_PERIOD
+
+
+#
+# System level modules to be synthesized
+#
+define_hls_module test ../src/test.cpp
+
+
+#
+# Testbench or system level modules
+#
+define_system_module tb ../tb/system.cpp ../tb/sc_main.cpp
+
+######################################################################
+# HLS and Simulation configurations
+######################################################################
+set DEFAULT_ARGV ""
+
+foreach dma [list 32 64] {
+    define_io_config * IOCFG_DMA$dma -DDMA_WIDTH=$dma
+
+    define_system_config tb TESTBENCH_DMA$dma -io_config IOCFG_DMA$dma
+
+    define_sim_config "BEHAV_DMA$dma" "test BEH" "tb TESTBENCH_DMA$dma" -io_config IOCFG_DMA$dma -argv $DEFAULT_ARGV
+
+    foreach cfg [list BASIC] {
+	set cname $cfg\_DMA$dma
+	define_hls_config test $cname -io_config IOCFG_DMA$dma --clock_period=$CLOCK_PERIOD $COMMON_HLS_FLAGS -DHLS_DIRECTIVES_$cfg
+	if {$TECH_IS_XILINX == 1} {
+	    define_sim_config "$cname\_V" "test RTL_V $cname" "tb TESTBENCH_DMA$dma" -io_config IOCFG_DMA$dma -argv $DEFAULT_ARGV -verilog_top_modules glbl
+	} else {
+	    define_sim_config "$cname\_V" "test RTL_V $cname" "tb TESTBENCH_DMA$dma" -io_config IOCFG_DMA$dma -argv $DEFAULT_ARGV
+	}
+    }
+}
+
+#
+# Compile Flags
+#
+set_attr hls_cc_options "$INCLUDES"
+
+#
+# Simulation Options
+#
+use_systemc_simulator xcelium
+set_attr cc_options "$INCLUDES -DCLOCK_PERIOD=$SIM_CLOCK_PERIOD"
+# enable_waveform_logging -vcd
+set_attr end_of_sim_command "make saySimPassed"

accelerators/stratus_hls/test_stratus/hw/memlist.txt

@@ -0,0 +1,4 @@
+test_plm_block_in_dma32 1024 32 1w:0r 0w:1r
+test_plm_block_out_dma32 1024 32 1w:0r 0w:1r
+test_plm_block_in_dma64 1024 32 2w:0r 0w:1r
+test_plm_block_out_dma64 1024 32 1w:0r 0w:2r

accelerators/stratus_hls/test_stratus/hw/sim/.gitignore

@@ -0,0 +1 @@
+test

accelerators/stratus_hls/test_stratus/hw/sim/Makefile

@@ -0,0 +1 @@
+include ../../../common/systemc.mk