Skip to content
This repository was archived by the owner on Nov 4, 2024. It is now read-only.

Commit db75040

Browse files
iamkarthikbkvamshimahendraVamshi
authored
Compressed instruction support for rvopcodesdecoder (#73)
* fixed isac for compressed instr * fixed isac for compressed instr * Update rvopcodesdecoder.py Signed-off-by: Mahendra Vamshi A <[email protected]> * Update rvopcodesdecoder.py added immideate feilds for compressed instructions Signed-off-by: Mahendra Vamshi A <[email protected]> * remove extra comments in the decoder. Signed-off-by: Karthik B K <[email protected]> * minor cleanup Signed-off-by: Karthik B K <[email protected]> * Update CHANGELOG.md Signed-off-by: Karthik B K <[email protected]> * Update setup.cfg to 0.18.0 Signed-off-by: Karthik B K <[email protected]> * Update setup.py to 0.18.0 Signed-off-by: Karthik B K <[email protected]> * Update __init__.py to version 0.18.0 Signed-off-by: Karthik B K <[email protected]> --------- Signed-off-by: Mahendra Vamshi A <[email protected]> Signed-off-by: Karthik B K <[email protected]> Co-authored-by: vamshi <vamshi@LAPTOP-MTLHJ5FE> Co-authored-by: Mahendra Vamshi A <[email protected]>
1 parent a4b25fa commit db75040

File tree

5 files changed

+198
-10
lines changed

5 files changed

+198
-10
lines changed

‎CHANGELOG.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22

33
This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
44

5+
## [0.18.0] - 2023-07-26
6+
- Add support to decode compressed instructions
57

68
## [0.17.0] - 2022-10-25
79
- Improve data propagation reports to capture multiple signature updates per coverpoint

‎riscv_isac/__init__.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,5 +4,5 @@
44

55
__author__ = """InCore Semiconductors Pvt Ltd"""
66
__email__ = '[email protected]'
7-
__version__ = '0.17.0'
7+
__version__ = '0.18.0'
88

‎riscv_isac/data/rvopcodesdecoder.py‎

Lines changed: 193 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -329,9 +329,7 @@ def decode(self, instrObj_temp):
329329
instr = None
330330

331331
temp_instrobj = instrObj_temp
332-
333332
mcode = temp_instrobj.instr
334-
335333
name_args = disassembler.get_instr(disassembler.INST_DICT, mcode)
336334
if not name_args:
337335
name_args = instr
@@ -355,25 +353,25 @@ def decode(self, instrObj_temp):
355353
if file_name in ['rv_f', 'rv64_f', 'rv_d','rv64_d']:
356354
reg_type = 'f'
357355
for arg in args[:-1]:
358-
if arg == 'rd':
356+
if 'rd' in arg:
359357
treg = reg_type
360358
if any([instr_name.startswith(x) for x in [
361359
'fcvt.w','fcvt.l','fmv.s','fmv.d','flt','feq','fle','fclass']]):
362360
treg = 'x'
363361
temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), treg)
364-
if arg == 'rs1':
362+
if 'rs1' in arg:
365363
treg = reg_type
366364
if any([instr_name.startswith(x) for x in [
367365
'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
368366
treg = 'x'
369367
temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg)
370-
if arg == 'rs2':
368+
if 'rs2' in arg:
371369
treg = reg_type
372370
temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg)
373-
if arg == 'rs3':
371+
if 'rs3' in arg:
374372
treg = reg_type
375373
temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), treg)
376-
if arg == 'csr':
374+
if 'csr' in arg:
377375
temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2)
378376
if arg == 'shamt':
379377
temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2)
@@ -420,6 +418,194 @@ def decode(self, instrObj_temp):
420418
imm = imm[0] + imm_temp[-1] + imm[1:] + imm_temp[0:4] + '0'
421419
else:
422420
imm = imm + imm_temp
421+
if arg == 'c_uimm7hi':
422+
imm_temp = get_arg_val(arg)(mcode)
423+
if imm:
424+
imm = imm[-1] + imm_temp + imm[0] + '00'
425+
else:
426+
imm = imm_temp + imm
427+
if arg == 'c_uimm7lo':
428+
imm_temp = get_arg_val(arg)(mcode)
429+
if imm:
430+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
431+
else:
432+
imm = imm + imm_temp
433+
434+
if arg == 'c_uimm8lo':
435+
imm_temp = get_arg_val(arg)(mcode)
436+
if imm:
437+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
438+
else:
439+
imm = imm + imm_temp
440+
if arg == 'c_uimm8hi':
441+
imm_temp = get_arg_val(arg)(mcode)
442+
if imm:
443+
imm = imm[-1] + imm_temp + imm[0] + '00'
444+
else:
445+
imm = imm_temp + imm
446+
447+
if arg == 'c_uimm9lo':
448+
imm_temp = get_arg_val(arg)(mcode)
449+
if imm:
450+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
451+
else:
452+
imm = imm + imm_temp
453+
elif arg == 'c_uimm9hi':
454+
imm_temp = get_arg_val(arg)(mcode)
455+
if imm:
456+
imm = imm[-1] + imm_temp + imm[0] + '00'
457+
else:
458+
imm = imm_temp + imm
459+
460+
elif arg == 'c_nzimm6lo':
461+
imm_temp = get_arg_val(arg)(mcode)
462+
if imm:
463+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
464+
else:
465+
imm = imm + imm_temp
466+
elif arg == 'c_nzimm6hi':
467+
imm_temp = get_arg_val(arg)(mcode)
468+
if imm:
469+
imm = imm[-1] + imm_temp + imm[0] + '00'
470+
else:
471+
imm = imm_temp + imm
472+
473+
elif arg == 'c_imm6lo':
474+
imm_temp = get_arg_val(arg)(mcode)
475+
if imm:
476+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
477+
else:
478+
imm = imm + imm_temp
479+
elif arg == 'c_imm6hi':
480+
imm_temp = get_arg_val(arg)(mcode)
481+
if imm:
482+
imm = imm[-1] + imm_temp + imm[0] + '00'
483+
else:
484+
imm = imm_temp + imm
485+
486+
elif arg == 'c_nzimm10hi':
487+
imm_temp = get_arg_val(arg)(mcode)
488+
if imm:
489+
imm = imm[-1] + imm_temp + imm[0] + '00'
490+
else:
491+
imm = imm_temp + imm
492+
elif arg == 'c_nzimm10lo':
493+
imm_temp = get_arg_val(arg)(mcode)
494+
if imm:
495+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
496+
else:
497+
imm = imm + imm_temp
498+
499+
elif arg == 'c_nzimm18hi':
500+
imm_temp = get_arg_val(arg)(mcode)
501+
if imm:
502+
imm = imm[-1] + imm_temp + imm[0] + '00'
503+
else:
504+
imm = imm_temp + imm
505+
elif arg == 'c_nzimm18lo':
506+
imm_temp = get_arg_val(arg)(mcode)
507+
if imm:
508+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
509+
else:
510+
imm = imm + imm_temp
511+
512+
elif arg == 'c_imm12':
513+
imm_temp = get_arg_val(arg)(mcode)
514+
if imm:
515+
imm = imm[-1] + imm_temp + imm[0] + '00'
516+
else:
517+
imm = imm_temp + imm
518+
519+
elif arg == 'c_bimm9lo':
520+
imm_temp = get_arg_val(arg)(mcode)
521+
if imm:
522+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
523+
else:
524+
imm = imm + imm_temp
525+
elif arg == 'c_bimm9hi':
526+
imm_temp = get_arg_val(arg)(mcode)
527+
if imm:
528+
imm = imm[-1] + imm_temp + imm[0] + '00'
529+
else:
530+
imm = imm_temp + imm
531+
532+
elif arg == 'c_nzuimm5':
533+
imm_temp = get_arg_val(arg)(mcode)
534+
imm = imm_temp + imm
535+
536+
elif arg == 'c_nzuimm6lo':
537+
imm_temp = get_arg_val(arg)(mcode)
538+
if imm:
539+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
540+
else:
541+
imm = imm + imm_temp
542+
543+
544+
elif arg == 'c_nzuimm6hi':
545+
imm_temp = get_arg_val(arg)(mcode)
546+
if imm:
547+
imm = imm[-1] + imm_temp + imm[0] + '00'
548+
else:
549+
imm = imm_temp + imm
550+
551+
elif arg == 'c_uimm8splo':
552+
imm_temp = get_arg_val(arg)(mcode)
553+
if imm:
554+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
555+
else:
556+
imm = imm + imm_temp
557+
558+
elif arg == 'c_uimm8sphi':
559+
imm_temp = get_arg_val(arg)(mcode)
560+
if imm:
561+
imm = imm[-1] + imm_temp + imm[0] + '00'
562+
else:
563+
imm = imm_temp + imm
564+
565+
elif arg == 'c_uimm8sp_s':
566+
imm_temp = get_arg_val(arg)(mcode)
567+
imm = imm[-1] + imm_temp + imm[0] + '00'
568+
569+
elif arg == 'c_uimm10splo':
570+
imm_temp = get_arg_val(arg)(mcode)
571+
if imm:
572+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
573+
else:
574+
imm = imm + imm_temp
575+
576+
elif arg == 'c_uimm10sphi':
577+
imm_temp = get_arg_val(arg)(mcode)
578+
if imm:
579+
imm = imm[-1] + imm_temp + imm[0] + '00'
580+
else:
581+
imm = imm_temp + imm
582+
583+
elif arg == 'c_uimm9splo':
584+
imm_temp = get_arg_val(arg)(mcode)
585+
if imm:
586+
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
587+
else:
588+
imm = imm + imm_temp
589+
590+
elif arg == 'c_uimm9sphi':
591+
imm_temp = get_arg_val(arg)(mcode)
592+
if imm:
593+
imm = imm[-1] + imm_temp + imm[0] + '00'
594+
else:
595+
imm = imm_temp + imm
596+
597+
elif arg == 'c_uimm10sp_s':
598+
imm_temp = get_arg_val(arg)(mcode)
599+
imm = imm_temp + imm
600+
601+
elif arg == 'c_uimm9sp_s':
602+
imm_temp = get_arg_val(arg)(mcode)
603+
imm = imm_temp + imm
604+
605+
elif arg == 'c_nzuimm10':
606+
imm_temp = get_arg_val(arg)(mcode)
607+
imm = imm_temp + imm
608+
423609
if imm:
424610
numbits = len(imm)
425611
temp_instrobj.imm = disassembler.twos_comp(int(imm, 2), numbits)

‎setup.cfg‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
[bumpversion]
2-
current_version = 0.17.0
2+
current_version = 0.18.0
33
commit = True
44
tag = True
55

‎setup.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ def read_requires():
2626

2727
setup(
2828
name='riscv_isac',
29-
version='0.17.0',
29+
version='0.18.0',
3030
description="RISC-V ISAC",
3131
long_description=readme + '\n\n',
3232
classifiers=[

0 commit comments

Comments
 (0)