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Close the gap between "unit tests pass" and "compiler actually works end-to-end."
Task
Priority
Status
Calculator demo (add, sub, mul, div)
P0
Open
Control flow through full compile path
P0
Open
Memory operations through full compile path
P0
Open
WAST integration test runner
P1
Open
Success Criteria:
synth compile calculator.wat --all-exports --cortex-m -o calculator.elf works
synth verify calculator.wat calculator.elf passes
Control flow (if/else, loop, br) compiles end-to-end
Memory ops (load/store) compile end-to-end
Phase B: CI/CD & Automated Testing (P0)
Task
Priority
Status
GitHub Actions: cargo test --workspace
P0
Open
GitHub Actions: cargo clippy --workspace
P0
Open
GitHub Actions: cargo fmt --check
P0
Open
GitHub Actions: Z3 verification tests
P1
Open
Pre-commit hooks
P2
Open
Success Criteria:
PRs run tests automatically
Code quality checks enforced
Z3 verification tests run weekly or on synth-verify changes
Phase C: Testing Infrastructure (P1)
Task
Priority
Status
QEMU ARM testing harness
P0
Open
Renode integration (config files exist)
P1
Open
W3C spec test suite adapter (267 files exist)
P2
Open
Success Criteria:
Compiled ELFs execute on QEMU and produce correct results
Spec test conformance percentage tracked
Phase D: External Backends (P2)
Task
Priority
Status
w2c2 backend: compile_module()
P0
Open
aWsm backend: compile_module()
P1
Open
wasker backend: compile_module()
P1
Open
Backend comparison tests
P2
Open
Phase E: Bazel & Build (P2)
Task
Priority
Status
Add synth-memory to BUILD.bazel
P0
Open
Verify bazel build //crates:synth
P1
Open
Verify bazel test //...
P1
Open
Phase F: Authoritative ISA Semantics (P3, Research)
Task
Priority
Status
Evaluate Sail ARM integration
P0
Research
RISC-V via sail-riscv
P1
Research
Goal: Replace hand-written ARM semantics with machine-readable specs derived from ARM's own ISA specification, making verification proofs authoritative.