Add Verilator Setup

[stevemikaeldouglas]

Why this doesn't support opensource tools such as Verilator

[paulsc96]

Generally speaking, Cheshire can be used with open-source EDA and simulation tools. It is even fully synthesizable using yosys-slang.

As for Verilator, we simply don't have an upstream simulation setup for it. It's a lot of work because Verilator does not support many standard Systemverilog verification constructs. So it's not a matter of Cheshire not "supporting" Verilator, but Verilator not supporting SystemVerilog correctly. Feel free to open an issue here: https://github.com/verilator/verilator

If you want a setup working around Verilator's insufficiencies, contributions are welcome.

[paulsc96]

If you need Verilator in a hurry and are fine with JTAG preloading, SPM linking, and UART output only, check out the WIP branch paulsc/vl:

make all
make VERILATOR=/path/to/verilator verilator-all # takes around 50 mins (8 cores, clang)
target/sim/verilator/Vtb_cheshire_soc +BINARY=sw/tests/helloworld.spm.elf

[cousteaulecommandant]

Verilator does not support many standard Systemverilog verification constructs.

What kind of constructs are we talking about here? Hardware design constructs (synthesizable)? Timing, delays, clock generation? SystemVerilog Assertions? Coverage analysis? UVM compatibility? Or is it a bit of everything? I know there is currently an ongoing effort in Verilator to support some of these.

[paulsc96]

There is indeed. Unfortunately, as it stands, it cannot properly handle our testbench yet (see #182). Apart from the SPI Flash model being unsupported, some fundamental testbench constructs result in verilated code that either takes absurd amounts of time or RAM to compile, depending on what features are removed and what flags are used. So I am afraid that support for regular event-based testbenches in Verilator is still experimental at best.