Hello,
A while ago, I reverse engineered how multiplication inside of the MIPS CPU core works. This was done by issuing carefully timed writes to the LO/HI registers after starting the operation. I noticed that the ranges used to determine timing were different than what Martin had in his docs. I attempted to contact him directly but it was a giant pain, and I gave up on it. Since this should be easier, I'm just making it known that this exists and is 100% verified on my SCPH-7501 and SCPH-5501 consoles.
If there's interest, I can include a write-up of the DIV/DIVU operations as well.
Hello,
A while ago, I reverse engineered how multiplication inside of the MIPS CPU core works. This was done by issuing carefully timed writes to the
LO/HIregisters after starting the operation. I noticed that the ranges used to determine timing were different than what Martin had in his docs. I attempted to contact him directly but it was a giant pain, and I gave up on it. Since this should be easier, I'm just making it known that this exists and is 100% verified on mySCPH-7501andSCPH-5501consoles.If there's interest, I can include a write-up of the
DIV/DIVUoperations as well.