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Use 16-channel virtual mux on Cosmo (#2154)
Right now, the Cosmo FPGAs (main and front) both pretend to contain a set of PCA9545 muxes. This PR switches to a **single** virtual 16-channel mux, which reduces writes (since we no longer need to deactivate virtual mux _N_ before activating virtual mux _M_). Having a single mux also makes it more logically consistent to have a single reset pin, see oxidecomputer/hardware-cosmo#619 Finally, it gives us a place to put the delay required by the physical switches' timing that _doesn't_ mess with our existing driver. --------- Co-authored-by: Nathanael Huffman <[email protected]>
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‎app/cosmo/base.toml

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‎drv/cosmo-seq-server/cosmo-hp/README.md

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FPGA images and collateral are generated from:
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[this sha](https://github.com/oxidecomputer/quartz/commit/ac70329388b36815bc405b58b5260a060bbfa953)
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[release](https://api.github.com/repos/oxidecomputer/quartz/releases/226010645)
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[this sha](https://github.com/oxidecomputer/quartz/commit/0d094c19ea381fdf4aa8f0b0fc7e5f2a33a37506)
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[release](https://api.github.com/repos/oxidecomputer/quartz/releases/234047862)

‎drv/cosmo-seq-server/cosmo-hp/cosmo_hp.bz2

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‎drv/i2c-types/src/lib.rs

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@@ -224,4 +224,12 @@ pub enum Segment {
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S6 = 6,
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S7 = 7,
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S8 = 8,
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S9 = 9,
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S10 = 10,
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S11 = 11,
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S12 = 12,
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S13 = 13,
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S14 = 14,
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S15 = 15,
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S16 = 16,
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}

‎drv/spartan7-loader/cosmo-seq/README.md

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FPGA images and collateral are generated from:
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[this sha](https://github.com/oxidecomputer/quartz/commit/1c58def4fc932e2f42f74573494678a056925da9)
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[release](https://api.github.com/repos/oxidecomputer/quartz/releases/231238503)
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[this sha](https://github.com/oxidecomputer/quartz/commit/0d094c19ea381fdf4aa8f0b0fc7e5f2a33a37506)
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[release](https://api.github.com/repos/oxidecomputer/quartz/releases/234047771)

‎drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2

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‎drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json

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},
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{
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"type": "addrmap",
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"addr_span_bytes": 84,
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"addr_span_bytes": 88,
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"inst_name": "sequencer",
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"orig_type_name": "sequencer_regs",
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"addr_offset": 768,

‎drv/spartan7-loader/cosmo-seq/debug_regs.json

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{
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"name": "t6_sequencer",
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"value": 11
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},
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{
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"name": "mux1_sel",
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"value": 12
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},
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{
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"name": "mux2_sel",
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"value": 13
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},
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{
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"name": "mux3_sel",
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"value": 14
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}
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]
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},
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{
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"name": "t6_sequencer",
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"value": 11
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},
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{
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"name": "mux1_sel",
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"value": 12
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},
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{
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"name": "mux2_sel",
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"value": 13
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},
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{
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"name": "mux3_sel",
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"value": 14
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}
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]
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},
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{
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"name": "t6_sequencer",
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"value": 11
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},
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{
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"name": "mux1_sel",
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"value": 12
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},
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{
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"name": "mux2_sel",
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"value": 13
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},
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{
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"name": "mux3_sel",
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"value": 14
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}
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]
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},
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{
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"name": "t6_sequencer",
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"value": 11
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},
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{
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"name": "mux1_sel",
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"value": 12
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},
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{
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"name": "mux2_sel",
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"value": 13
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},
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{
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"name": "mux3_sel",
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"value": 14
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}
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]
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}

‎drv/spartan7-loader/cosmo-seq/sequencer_regs.json

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{
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"type": "addrmap",
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"addr_span_bytes": 84,
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"addr_span_bytes": 88,
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"inst_name": "sequencer_regs",
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"addr_offset": 0,
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"children": [
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},
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{
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"type": "reg",
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"inst_name": "rail_enables",
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"inst_name": "amd_pwgdout_fedges",
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"addr_offset": 48,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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"inst_name": "counts",
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"lsb": 0,
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"msb": 7,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": "wclr",
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"desc": "Falling edge counter of AMD's PowerGDOUT output while in A0/A0HP. Saturates at 255. Cleared by any write or starting a new power up"
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "rail_enables",
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"addr_offset": 52,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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{
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"type": "reg",
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"inst_name": "rail_pgs",
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"addr_offset": 52,
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"addr_offset": 56,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "rail_pgs_max_hold",
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"addr_offset": 56,
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"addr_offset": 60,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "sp5_readbacks",
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"addr_offset": 60,
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"addr_offset": 64,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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"se_onread": null,
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"se_onwrite": null,
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"desc": "pwr_btn_l live status, (From FPGA to SP5)"
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},
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{
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"type": "field",
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"inst_name": "pwrgd_out",
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"lsb": 9,
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"msb": 9,
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"reset": null,
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"sw_access": "r",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "pwrgd_out live status, (From SP5 to FPGA)"
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "nic_readbacks",
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"addr_offset": 64,
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"addr_offset": 68,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "debug_enables",
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"addr_offset": 68,
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"addr_offset": 72,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "nic_overrides",
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"addr_offset": 72,
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"addr_offset": 76,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "ignition_control",
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"addr_offset": 76,
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"addr_offset": 80,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "pcie_clk_ctrl",
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"addr_offset": 80,
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"addr_offset": 84,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [

‎drv/stm32xx-i2c/src/lib.rs

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pub mod ltc4306;
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pub mod max7358;
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pub mod oximux16;
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pub mod pca9545;
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pub mod pca9548;
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