Merge pull request #410 from AYYAZmayo/main

EDA-3246: Converting O_BUF_DS to O_BUFT_DS

Author: AYYAZmayo

src/synth_rapidsilicon.cc

@@ -5358,6 +5358,12 @@ static void show_sig(const RTLIL::SigSpec &sig)
 
                     if (!cell->hasParam(RTLIL::escape_id("WEAK_KEEPER")))
                         cell->setParam(RTLIL::escape_id("WEAK_KEEPER"), stringf("NONE"));
+
+                    if (!cell->hasParam(RTLIL::escape_id("IOSTANDARD")))
+                        cell->setParam(RTLIL::escape_id("IOSTANDARD"), stringf("DEFAULT"));
+
+                    if (!cell->hasParam(RTLIL::escape_id("DIFFERENTIAL_TERMINATION")))
+                        cell->setParam(RTLIL::escape_id("DIFFERENTIAL_TERMINATION"), stringf("TRUE"));
                 }
 
                 if (cell->type == RTLIL::escape_id("I_BUF_DS")){
@@ -5886,7 +5892,26 @@ static void show_sig(const RTLIL::SigSpec &sig)
             cell->setPort(ID::T, State::S1);
         }
     }
+   // Replace all O_BUF_DS cells by O_BUFT_DS equivalent.
+    //
+    // To correctly configure the GB in O_BUF_DS mode, we need to use
+    // the O_BUFT_DS and set the enable signal "T" to 1.
+    //
+    void map_o_buf_ds_to_o_buft_ds(RTLIL::Module *top_module)
+    {
+        for (auto cell : top_module->cells()) {
 
+            if (cell->type != RTLIL::escape_id("O_BUF_DS")) {
+                continue;
+            }
+
+            cell->type = RTLIL::escape_id("O_BUFT_DS");
+
+            // Add extra port 'T' set to 1'b1
+            //
+            cell->setPort(ID::T, State::S1);
+        }
+    }
     // Remove I_BUF and O_BUF and replace by assigns
     // This is usefull for instance when we start from a bad implementation
     // of I_BUF/O_Buf like in test case : 
@@ -9167,7 +9192,6 @@ void collect_clocks (RTLIL::Module* module,
            run("techmap -map" + techMaplutArgs);
 #endif
 
-           check_blackbox_param();
 
            if (legalize_ram_clk_ports) {
              legalize_all_tdp_ram_clock_ports();
@@ -9191,6 +9215,8 @@ void collect_clocks (RTLIL::Module* module,
         // after calling 'rewire_obuft'.
         //
         map_obuf_to_obuft(_design->top_module());
+        map_o_buf_ds_to_o_buft_ds(_design->top_module());
+        check_blackbox_param();
 
         // Eventually performs post synthesis clean up
         //