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1. IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA), in IEEE STD 1481-2009 , vol., no., pp.1-658, 11 March 2010.
2. Esmaieli, E.; Sedaghat, Y.; Peiravi, A. Fanout-Based Reliability Model for SER Estimation in Combinational Circuits, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 1, pp. 228-240, Jan. 2025.
3. Hwang, M.-E.; Jung, S.-O.; Roy, K. Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 7, pp. 1428-1441, July 2009.
4. Huang, W.; Du, J.; Hua, W.; Bi, K.; Fan, Q. A Hybrid Model-Based Diagnosis Approach for Open-Switch Faults in PMSM Drives, in IEEE Transactions on Power Electronics, vol. 37, no. 4, pp. 3728-3732, April 2022.
5. Fu, R.; Wille, R.; Yoshikawa, N.; Ho, T.-Y. Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.