Merge branch 'dev' of https://github.com/mabrains/IHP-Open-PDK into devices_ngspice_testing

Author: FaragElsayed2

README.md

@@ -27,6 +27,12 @@ release was derived have been used to create many designs that have been
 successfully manufactured in significant quantities, the open source PDK
 is not intended to be used for production at this moment.
 
+# Documentation
+
+Comprehensive documentation for the IHP Open Source PDK is available on [ReadTheDocs](https://ihp-open-pdk.readthedocs.io/en/latest/).
+
+The documentation provides detailed information on PDK installation, setup for supported EDA tools, device libraries, layout rules, process specifications and design flow examples. It is the recommended starting point for users who want to explore the PDK structure, simulation models, layout design environments, etc.
+
 # SG13G2 Process Node
 
 SG13G2 is a high performance BiCMOS technology with a 0.13 μm CMOS process. It contains bipolar
@@ -62,10 +68,15 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * GDSII
 * KLayout tool data:
     * layer property and tech files
-    * DRC rules (minimal/maximal set)
+    * DRC rules
     * LVS rules
-    * PyCells (1st priority)
+    * PyCells
     * XSection initial settings
+    * 2.5D viewer configuration
+* Magic tool data:
+    * tech files, parasitic extraction rules
+    * DRC rules
+    * LVS rules
 * MOS/HBT/Passive device models for ngspice/Xyce
 * xschem: primitive device symbols, settings and testbenches
 * Qucs-S: primitive device symbols, settings and testbenches
@@ -91,12 +102,17 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
 * KLayout
     * Download: https://www.klayout.de/build.html
     * Source: https://github.com/KLayout/klayout
+* Magic
+    * Download: http://opencircuitdesign.com/magic/download.html
+    * Source: https://github.com/RTimothyEdwards/magic
 * OpenEMS
     * Source: https://github.com/thliebig/openEMS-Project
 * OpenROAD
     * Source: https://github.com/The-OpenROAD-Project/OpenROAD
 * OpenROAD-flow-scripts
     * Source: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
+* LibreLane
+    * Source: https://github.com/librelane/librelane
 
 ## Tool versions (tested with)
 [versions.txt](versions.txt)

ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef

@@ -425,7 +425,7 @@ Via  Via1_s DEFAULT
       RECT -0.19 -0.19 0.19 0.19 ;
   END Via1_s
 
-####### Definitions of Via1 duoble cut ########
+####### Definitions of Via1 double cut ########
 
 Via Via1_DC1B DEFAULT
     RESISTANCE 20.0 ;
@@ -616,7 +616,7 @@ Via  Via2_s DEFAULT
       RECT -0.19 -0.19 0.19 0.19 ;
   END Via2_s
 
-#######  Definitions of Via2 duoble cut ##############
+#######  Definitions of Via2 double cut ##############
 
 Via Via2_DC1B DEFAULT
     RESISTANCE 20.0 ;
@@ -807,7 +807,7 @@ Via  Via3_s DEFAULT
       RECT -0.19 -0.19 0.19 0.19 ;
   END Via3_s
 
-#######  Definitions of Via3 duoble cut ##############
+#######  Definitions of Via3 double cut ##############
 
 Via Via3_DC1B DEFAULT
     RESISTANCE 20.0 ;
@@ -998,7 +998,7 @@ Via  Via4_s DEFAULT
       RECT -0.19 -0.19 0.19 0.19 ;
   END Via4_s
 
-#######  Definitions of Via4 duoble cut ##############
+#######  Definitions of Via4 double cut ##############
 
 Via Via4_DC1B DEFAULT
     RESISTANCE 20.0 ;

ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/rhigh_code.py

@@ -476,7 +476,7 @@ def genLayout(self):
         # create virtuel l for CbResCalc
         lcalc = (l*stripes+contactpush*2+lcor)/stripes
         resistance = CbResCalc('R', 0, lcalc*1e-6, w*1e-6, b, ps*1e-6, Cell)
-        labeltext = 'rpnd r={0:.3f}'.format(resistance)
+        labeltext = 'rhigh r={0:.3f}'.format(resistance)
         labelpos = Point(w/2, l/2)
         labelheight = 0.1
         if w > l :

ihp-sg13g2/libs.tech/klayout/tech/drc/rule_decks/5_14_cont.drc

@@ -43,10 +43,17 @@ if FEOL
     # Rule Cnt.c: Min. Activ enclosure of Cont is 0.07 um
     logger.info('Executing rule Cnt.c')
     cnt_c_value = drc_rules['Cnt_c'].to_f
-    cnt_c_l = cont_sq.enclosed(activ_drw, cnt_c_value.um, euclidian)
+    cnt_c_l = cont_sq.not(digibnd_drw).enclosed(activ_drw, cnt_c_value.um, euclidian)
     cnt_c_l.output('Cnt.c', "5.14. Cnt.c Min. Activ enclosure of Cont is #{cnt_c_value} um")
     cnt_c_l.forget
 
+    # Rule Cnt.c: Min. Activ enclosure of Cont (Inside DigiBnd) is 0.05 um
+    logger.info('Executing rule Cnt.c')
+    cnt_c_digibnd_value = drc_rules['Cnt_c_digibnd'].to_f
+    cnt_c_l = cont_sq.and(digibnd_drw).enclosed(activ_drw, cnt_c_digibnd_value.um, euclidian)
+    cnt_c_l.output('Cnt.c.digibnd', "8.1.2. Cnt.c.digibnd Min. Activ enclosure of Cont (Inside DigiBnd) is #{cnt_c_digibnd_value} um")
+    cnt_c_l.forget
+
     # Rule Cnt.d: Min. GatPoly enclosure of Cont is 0.07 um
     logger.info('Executing rule Cnt.d')
     cnt_d_value = drc_rules['Cnt_d'].to_f

ihp-sg13g2/libs.tech/klayout/tech/drc/rule_decks/main.drc

@@ -223,7 +223,7 @@ pwell = pwell_allowed.not(nwell_drw).not(digisub_gap)
 # nBulay
 nbulay_tables = %w[main nbulay nwell activfiller schottkydiode]
 if nbulay_tables.include?(TABLE_NAME)
-  nbulay_gen_sized = nwell_drw.sized(-1.5.um).sized(0.5.um)
+  nbulay_gen_sized = nwell_drw.sized(-1.495.um).sized(0.495.um)
   nbuLay_gen = nbulay_gen_sized.not(nbulay_block.join(res_drw))
   nbuLay_gen_nbulay = nbuLay_gen.join(nbulay_drw)
 end

ihp-sg13g2/libs.tech/klayout/tech/drc/rule_decks/sg13g2_tech_default.json

@@ -130,6 +130,7 @@
         "Cnt_b1": 0.2,
         "Cnt_b1_nr": 4,
         "Cnt_c": 0.07,
+        "Cnt_c_digibnd": 0.05,
         "Cnt_d": 0.07,
         "Cnt_e": 0.14,
         "Cnt_f": 0.11,

ihp-sg13g2/libs.tech/klayout/tech/drc/testing/gen_golden.py

@@ -483,6 +483,7 @@ def run_test_case(
         f"--run_dir={output_loc} "
         f"--run_mode=flat "
         f"--no_density "
+        f"--disable_extra_rules "
         f"> {pattern_log} 2>&1"
     )