Respond to reviewer comments re: in-line code comments

Author: chrisjbris

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -5066,10 +5066,11 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
   }
   case ISD::SELECT: {
     // fneg (select c, a, b) -> select c, (fneg a), (fneg b)
-    // This combine became necessary recently to prevent a regression caused by
-    // this patch legalising v2i32 xor. When adding this combine a case was
-    // added to performFNEGCombine to prevent this combine from being undone
-    // under certain conditions.
+    // This combine became necessary recently to prevent a regression in
+    // fneg-modifier-casting.ll caused by this patch legalising v2i32 xor.
+    // Specifically, additional instructions were added to the final codegen.
+    // When adding this combine a case was added to performFNEGCombine to
+    // prevent this combine from being undone under certain conditions.
     // TODO: Invert conditions of foldFreeOpFromSelect
     SDValue Cond = N0.getOperand(0);
     SDValue LHS = N0.getOperand(1);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5938,7 +5938,8 @@ SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
 }
 
 // Enable lowering of ROTR for vxi32 types. This is a workaround for a
-// regression caused by legalising v2i32 or.
+// regression in rotr.ll, whereby extra unnecessary instructions were added to
+// the final codegen caused by legalising v2i32 or.
 SDValue SITargetLowering::lowerROTR(SDValue Op, SelectionDAG &DAG) const {
   [[maybe_unused]] EVT VT = Op.getValueType();