|
| 1 | +########################################################################################################### |
| 2 | +# Copyright (C) 2021-2023 Intel Corporation |
| 3 | +# SPDX-License-Identifier: BSD-3-Clause |
| 4 | +########################################################################################################### |
| 5 | + |
| 6 | +# Icelake event list for platforms that don't have support for the fixed counter TMA events, e.g., some AWS |
| 7 | +# VMs. |
| 8 | +# Note that there are no more than 10 events per group. On these same platforms, the cpu-cycles fixed |
| 9 | +# counter is not supported so a general purpose counter will be used. |
| 10 | + |
| 11 | +cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, |
| 12 | +cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, |
| 13 | +cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, |
| 14 | +cpu/event=0xc3,umask=0x01,cmask=0x01,edge=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, |
| 15 | +cpu/event=0xc5,umask=0x00,period=50021,name='BR_MISP_RETIRED.ALL_BRANCHES'/, |
| 16 | +cpu/event=0xf1,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, |
| 17 | +cpu-cycles, |
| 18 | +ref-cycles, |
| 19 | +instructions; |
| 20 | + |
| 21 | +cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, |
| 22 | +cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, |
| 23 | +cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, |
| 24 | +cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL_PERIODS'/, |
| 25 | +cpu-cycles, |
| 26 | +ref-cycles, |
| 27 | +instructions; |
| 28 | + |
| 29 | +# events for TMA metrics without fixed counter support (group 1) |
| 30 | +cpu/event=0x9c,umask=0x01,name='IDQ_UOPS_NOT_DELIVERED.CORE'/, |
| 31 | +cpu/event=0xa4,umask=0x01,name='TOPDOWN.SLOTS_P'/, |
| 32 | +cpu/event=0x80,umask=0x04,name='ICACHE_DATA.STALLS'/, |
| 33 | +cpu/event=0x83,umask=0x04,name='ICACHE_TAG.STALLS'/, |
| 34 | +cpu/event=0x79,umask=0x30,name='IDQ.MS_SWITCHES'/, |
| 35 | +cpu/event=0x87,umask=0x01,name='DECODE.LCP'/, |
| 36 | +cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, |
| 37 | +cpu-cycles, |
| 38 | +ref-cycles, |
| 39 | +instructions; |
| 40 | + |
| 41 | +# events for TMA metrics without fixed counter support (group 2) |
| 42 | +cpu/event=0xab,umask=0x02,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, |
| 43 | +cpu/event=0xa4,umask=0x02,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, |
| 44 | +cpu/event=0x0D,umask=0x01,name='INT_MISC.CLEARS_COUNT'/, |
| 45 | +cpu/event=0xc2,umask=0x02,name='UOPS_RETIRED.SLOTS'/, |
| 46 | +cpu/event=0xd0,umask=0x83,name='MEM_INST_RETIRED.ANY'/, |
| 47 | +cpu/event=0xc4,umask=0x00,name='BR_INST_RETIRED.ALL_BRANCHES'/, |
| 48 | +cpu/event=0x9c,umask=0x01,cmask=0x05,period=1000003,name='IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE'/, |
| 49 | +cpu-cycles, |
| 50 | +ref-cycles, |
| 51 | +instructions; |
| 52 | + |
| 53 | +cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, |
| 54 | +cpu/event=0xa3,umask=0x0C,cmask=0x0C,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, |
| 55 | +cpu/event=0xa3,umask=0x14,cmask=0x14,period=2000003,name='CYCLE_ACTIVITY.STALLS_MEM_ANY'/, |
| 56 | +cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, |
| 57 | +cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, |
| 58 | +cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, |
| 59 | +cpu/event=0xa6,umask=0x04,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL'/, |
| 60 | +cpu-cycles, |
| 61 | +ref-cycles, |
| 62 | +instructions; |
| 63 | + |
| 64 | +cpu/event=0xd0,umask=0x21,cmask=0x00,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, |
| 65 | +cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, |
| 66 | +cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, |
| 67 | +cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, |
| 68 | +cpu-cycles, |
| 69 | +ref-cycles, |
| 70 | +instructions; |
| 71 | + |
| 72 | +cpu/event=0xa3,umask=0x05,cmask=0x05,period=1000003,name='CYCLE_ACTIVITY.STALLS_L2_MISS'/, |
| 73 | +cpu/event=0xa3,umask=0x06,cmask=0x06,period=1000003,name='CYCLE_ACTIVITY.STALLS_L3_MISS'/, |
| 74 | +cpu/event=0xa3,umask=0x0c,cmask=0x0c,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, |
| 75 | +cpu-cycles, |
| 76 | +ref-cycles, |
| 77 | +instructions; |
| 78 | + |
| 79 | +cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, |
| 80 | +cpu/event=0x79,umask=0x04,cmask=0x05,period=2000003,name='IDQ.MITE_CYCLES_OK'/, |
| 81 | +cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, |
| 82 | +cpu/event=0x79,umask=0x08,cmask=0x05,period=2000003,name='IDQ.DSB_CYCLES_OK'/, |
| 83 | +cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, |
| 84 | +cpu/event=0x14,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIVIDER_ACTIVE'/, |
| 85 | +cpu-cycles, |
| 86 | +ref-cycles, |
| 87 | +instructions; |
| 88 | + |
| 89 | +cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, |
| 90 | +cpu/event=0x79,umask=0x30,period=100003,name='IDQ.MS_UOPS'/, |
| 91 | +cpu/event=0x56,umask=0x01,period=100003,name='UOPS_DECODED.DEC0'/, |
| 92 | +cpu/event=0x56,umask=0x01,cmask=0x01,period=100003,name='UOPS_DECODED.DEC0:c1'/, |
| 93 | +cpu/event=0x0e,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/, |
| 94 | +cpu-cycles:k, |
| 95 | +ref-cycles:k, |
| 96 | +instructions:k; |
| 97 | + |
| 98 | +# OCR |
| 99 | +cpu/event=0xb7,umask=0x01,offcore_rsp=0x104000477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, |
| 100 | +cpu/event=0xb7,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, |
| 101 | +cpu/event=0x85,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, |
| 102 | +cpu/event=0x08,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, |
| 103 | +cpu-cycles, |
| 104 | +ref-cycles, |
| 105 | +instructions; |
| 106 | + |
| 107 | +cpu/event=0xb7,umask=0x01,offcore_rsp=0x1030000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, |
| 108 | +cpu/event=0xb7,umask=0x01,offcore_rsp=0x830000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, |
| 109 | +cpu/event=0xb7,umask=0x01,offcore_rsp=0x730000477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, |
| 110 | +cpu/event=0xb7,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, |
| 111 | +cpu/event=0x08,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, |
| 112 | +cpu/event=0x49,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, |
| 113 | +cpu-cycles, |
| 114 | +ref-cycles, |
| 115 | +instructions; |
| 116 | + |
| 117 | +# C6 |
| 118 | +cstate_core/c6-residency/; |
| 119 | +cstate_pkg/c6-residency/; |
| 120 | + |
| 121 | +# UPI |
| 122 | +upi/event=0x2,umask=0xf,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; |
| 123 | + |
| 124 | +# CHA |
| 125 | +cha/event=0x00,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; |
| 126 | + |
| 127 | +cha/event=0x35,umask=0xC8177E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, |
| 128 | +cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, |
| 129 | +cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, |
| 130 | +cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; |
| 131 | + |
| 132 | +cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; |
| 133 | +cha/event=0x35,umask=0xc88ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF'/, |
| 134 | +cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, |
| 135 | +cha/event=0x36,umask=0xC816FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/; |
| 136 | + |
| 137 | +cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD'/, |
| 138 | +cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, |
| 139 | +cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, |
| 140 | +cha/event=0x36,umask=0xC817FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; |
| 141 | + |
| 142 | +# memory read/writes |
| 143 | +imc/event=0x04,umask=0x0f,name='UNC_M_CAS_COUNT.RD'/, |
| 144 | +imc/event=0x04,umask=0x30,name='UNC_M_CAS_COUNT.WR'/; |
| 145 | + |
| 146 | +# power |
| 147 | +power/energy-pkg/, |
| 148 | +power/energy-ram/; |
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