[Feature Request] Add RV64I architecture support for 64-bit RISC-V instruction decoding #25
Description
Problem
Hard-coded Xlen::X32 in lib.rs:18-25 blocks 64-bit decoding.
Goals
- UI toggle for RV32I / RV64I
- Decode all RV64I instructions (ADDIW, SLLIW …)
- Handle 6-bit shift immediates
Tasks
- Make disassemble arch-aware
- Finish decoder (
process32.rs:248-261) - Add arch selector in UI
- 64-bit immediate & shift handling
- Tests & docs