From 6308fc3dd6008681e164b1f167b065d66a0026be Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 26 Aug 2025 17:24:35 +0200
Subject: [PATCH 1/2] write_mlir: emit src attributes from MLIR locations

---
 circt                     |  2 +-
 rtlil-emit/CMakeLists.txt |  1 +
 rtlil-emit/rtlil-emit.cpp | 11 +++++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/circt b/circt
index 1e3c587..98469e5 160000
--- a/circt
+++ b/circt
@@ -1 +1 @@
-Subproject commit 1e3c587854745563429dbf96d21332e721684575
+Subproject commit 98469e56ae665237b5e7a17f1f35e874725d9a67
diff --git a/rtlil-emit/CMakeLists.txt b/rtlil-emit/CMakeLists.txt
index 4b4b60b..faa10df 100644
--- a/rtlil-emit/CMakeLists.txt
+++ b/rtlil-emit/CMakeLists.txt
@@ -43,6 +43,7 @@ set(LIBS
         ${dialect_libs}
         ${conversion_libs}
         CIRCTRTLIL
+        CIRCTExportVerilog
         MLIRAnalysis
         MLIRCallInterfaces
         MLIRCastInterfaces
diff --git a/rtlil-emit/rtlil-emit.cpp b/rtlil-emit/rtlil-emit.cpp
index 9c982d2..ec4c80e 100644
--- a/rtlil-emit/rtlil-emit.cpp
+++ b/rtlil-emit/rtlil-emit.cpp
@@ -14,9 +14,11 @@
 #include "mlir/Target/LLVMIR/Export.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_os_ostream.h"
+#include "llvm/Support/raw_ostream.h"
 
 #include "circt/Dialect/RTLIL/RTLIL.h"
 #include "circt/Dialect/RTLIL/RTLILPasses.h"
+#include "circt/Conversion/ExportVerilog.h"
 
 // Malarkey - I think this is just not generally exposed?
 // TODO move elsewhere?
@@ -191,6 +193,14 @@ class RTLILifier {
       log_error("Unhandled RTLIL dialect value producing op\n");
     }
   }
+  void convertLoc(RTLIL::AttrObject* obj, const mlir::Location& loc) {
+    auto emitter = LocationEmitter(LoweringOptions::LocationInfoStyle::Plain, loc);
+    obj->attributes[RTLIL::ID::src] = RTLIL::Const(emitter.strref().data());
+    // std::string s;
+    // llvm::raw_string_ostream os(s);
+    // loc.print(os);
+    // obj->attributes[RTLIL::ID::src] = RTLIL::Const(os.str());
+  }
 
 public:
   RTLILifier(RTLIL::Design *d) : design(d) {}
@@ -207,6 +217,7 @@ class RTLILifier {
   void convert_cell(RTLIL::Module *mod, rtlil::CellOpInterface op) {
     RTLIL::Cell *c =
         mod->addCell(std::string(op.getCellName()), std::string(op.getCellType()));
+    convertLoc(c, op.getLoc());
     std::vector<std::string> signature;
     for (auto port : op.getCellPorts()) {
       std::string portName = llvm::cast<mlir::StringAttr>(port).str();

From af2a6daa11f3af05b61391643d9ccfa741ebc7e0 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 26 Aug 2025 17:26:07 +0200
Subject: [PATCH 2/2] write_mlir: add example

---
 rtlil-emit/example/not.mlir | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 rtlil-emit/example/not.mlir

diff --git a/rtlil-emit/example/not.mlir b/rtlil-emit/example/not.mlir
new file mode 100644
index 0000000..f6a1046
--- /dev/null
+++ b/rtlil-emit/example/not.mlir
@@ -0,0 +1,9 @@
+// yosys -m rtlil-emit/build/librtlil-emit.so -p "read_mlir rtlil-emit/example/not.mlir; dump"
+module {
+  module @"\\not" {
+    %0 = "rtlil.wire"() <{is_signed = false, name = "\\i1", port_id = 1 : i32, port_input = true, port_output = false, start_offset = 0 : i32, upto = false, width = 1 : i32}> : () -> !rtlil<val[1 : i32]>  loc ("foo.bar":1:2)
+    %1 = "rtlil.wire"() <{is_signed = false, name = "\\o1", port_id = 2 : i32, port_input = false, port_output = true, start_offset = 0 : i32, upto = false, width = 1 : i32}> : () -> !rtlil<val[1 : i32]>
+    "rtlil.cell"(%0, %1) <{name = "$2", parameters = [#rtlil<param "\\A_SIGNED" 0 : i32>, #rtlil<param "\\A_WIDTH" 1 : i32>, #rtlil<param "\\Y_WIDTH" 1 : i32>], ports = ["\\A", "\\Y"], type = "$not"}> : (!rtlil<val[1 : i32]>, !rtlil<val[1 : i32]>) -> ()
+  }
+}
+