Merge branch 'main' into addflaggemstest

Author: SabYic

.github/workflows/mthreads-build-and-test.yml

@@ -68,6 +68,7 @@ jobs:
           ./python/build/cmake.linux-x86_64-cpython-3.10/bin/triton-opt --pass-pipeline='builtin.module(convert-triton-to-tritongpu{target="cuda:CC" num-warps=4 threads-per-warp=32 num-ctas=1})'  ./test/bin/mthreads/add_kernel.ttir
           ./python/build/cmake.linux-x86_64-cpython-3.10/bin/triton-opt --convert-ub-to-llvm ./test/bin/mthreads/add_kernel.ttgir
           python3 -m pytest -s third_party/mthreads/python/test/unit
+          MUSA_VISIBLE_DEVICES=7 python3 -m pytest -s third_party/mthreads/python/test/unit
 
       - name: FlagTree Test with FlagGems
         shell: bash
@@ -78,4 +79,3 @@ jobs:
           cd FlagGems
           git checkout addflagtreetest
           python3 -m pytest -s --mode=quick --limit-cases=1 --skipped-unselected-nodeids
-

CMakeLists.txt

@@ -29,8 +29,6 @@ elseif(FLAGTREE_BACKEND STREQUAL "iluvatar")
     set (DEFAULT_PLUGIN_DIR "${Python3_SITELIB}/triton/_C")
   endif()
   add_definitions(-DDEFAULT_PLUGIN_DIR="${DEFAULT_PLUGIN_DIR}")
-  add_compile_options("-Wno-deprecated-declarations")
-  add_compile_options("-Wno-error=deprecated-declarations")
 elseif(FLAGTREE_BACKEND STREQUAL "mthreads")
   set(ENV{PATH} "$ENV{LLVM_SYSPATH}/bin:$ENV{PATH}")
   set(CMAKE_C_COMPILER clang)
@@ -62,6 +60,18 @@ function(get_flagtree_backend_lib lib_name output_lib)
   set(${output_lib} ${ret} PARENT_SCOPE)
 endfunction()
 
+# FLAGTREE SPEC TD FILE GET FUNC
+function(set_flagtree_backend_td output_td td_filename)
+  set(ret ${td_filename})
+  file(RELATIVE_PATH relative_path "${PROJECT_SOURCE_DIR}" "${CMAKE_CURRENT_SOURCE_DIR}")
+  get_filename_component(BACKEND_SPEC_ROOT "${BACKEND_SPEC_INCLUDE_DIR}" DIRECTORY)
+  set(BACKEND_SPEC_TD ${BACKEND_SPEC_ROOT}/${relative_path}/${td_filename})
+  if(EXISTS ${BACKEND_SPEC_TD})
+    set(ret ${BACKEND_SPEC_TD})
+  endif()
+  set(${output_td} ${ret} PARENT_SCOPE)
+endfunction()
+
 project(triton)
 include(CTest)
 
@@ -101,13 +111,14 @@ if(NOT WIN32)
 endif()
 
 # Compiler flags
+set(FLAGTREE_BACKEND_DIR ${PROJECT_SOURCE_DIR}/third_party/${FLAGTREE_BACKEND})
 ## flagtree spec include dir
-set(BACKEND_SPEC_INCLUDE_DIR ${PROJECT_SOURCE_DIR}/third_party/${FLAGTREE_BACKEND}/backend/flagtree_backend_specialization/include)
+set(BACKEND_SPEC_INCLUDE_DIR ${FLAGTREE_BACKEND_DIR}/backend/spec/include)
 if(FLAGTREE_BACKEND AND EXISTS ${BACKEND_SPEC_INCLUDE_DIR})
   include_directories(${BACKEND_SPEC_INCLUDE_DIR})
 endif()
 ## flagtree third_party include dir
-set(BACKEND_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/third_party/${FLAGTREE_BACKEND}/include)
+set(BACKEND_INCLUDE_DIR ${FLAGTREE_BACKEND_DIR}/include)
 if(FLAGTREE_BACKEND AND EXISTS "${BACKEND_INCLUDE_DIR}")
   include_directories(${BACKEND_INCLUDE_DIR})
 else()
@@ -118,9 +129,7 @@ set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -D__STDC_FORMAT_MACROS  -fPIC -std=gnu++17
 
 if(FLAGTREE_BACKEND STREQUAL "metax")
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DUSE_MACA -DUSE_MACA_OPAQUE_PTR -DUSE_BUILTIN -Wno-unused-result -Wno-attributes")
-endif()
-
-if(FLAGTREE_BACKEND STREQUAL "hcu")
+elseif(FLAGTREE_BACKEND STREQUAL "hcu")
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS  -fPIC -Wno-error=return-type -std=gnu++17")
 endif()
 
@@ -222,7 +231,7 @@ endif()
 # ------
 if(TRITON_BUILD_PYTHON_MODULE)
   message(STATUS "Adding Python module")
-  set(PYTHON_SRC_PATH ${CMAKE_CURRENT_SOURCE_DIR}/third_party/${FLAGTREE_BACKEND}/python/src)
+  set(PYTHON_SRC_PATH ${FLAGTREE_BACKEND_DIR}/python/src)
   if(NOT (FLAGTREE_BACKEND AND EXISTS "${PYTHON_SRC_PATH}"))
     set(PYTHON_SRC_PATH ${CMAKE_CURRENT_SOURCE_DIR}/python/src)
   endif()

README.md

@@ -1,11 +1,12 @@
 <div align="right"><a href="/README_cn.md">中文版</a></div>
 
-## FlagTree
+## <img width="30" height="30" alt="FlagTree-GitHub" src="https://github.com/user-attachments/assets/d8d24c81-6f46-4adc-94e2-b89b03afcb43" /> FlagTree
 
 FlagTree is an open source, unified compiler for multiple AI chips project dedicated to developing a diverse ecosystem of AI chip compilers and related tooling platforms, thereby fostering and strengthening the upstream and downstream Triton ecosystem. Currently in its initial phase, the project aims to maintain compatibility with existing adaptation solutions while unifying the codebase to rapidly implement single-repository multi-backend support. For upstream model users, it provides unified compilation capabilities across multiple backends; for downstream chip manufacturers, it offers examples of Triton ecosystem integration.
 
 ## Latest News
 
+* 2025/11/26 Add FlagTree_Backend_Specialization Unified Design Document [FlagTree_Backend_Specialization](reports/decoupling/).
 * 2025/09/30 Support flagtree_hints for shared memory on GPGPU.
 * 2025/09/29 SDK storage migrated to ksyuncs, improving download stability.
 * 2025/09/25 Support flagtree_hints for ascend backend compilation capability.

README_cn.md

@@ -1,10 +1,11 @@
 <div align="right"><a href="/README.md">English</a></div>
 
-## FlagTree
+## <img width="30" height="30" alt="FlagTree-GitHub" src="https://github.com/user-attachments/assets/d8d24c81-6f46-4adc-94e2-b89b03afcb43" /> FlagTree
 
 FlagTree 是面向多种 AI 芯片的开源、统一编译器。FlagTree 致力于打造多元 AI 芯片编译器及相关工具平台，发展和壮大 Triton 上下游生态。项目当前处于初期，目标是兼容现有适配方案，统一代码仓库，快速实现单仓库多后端支持。对于上游模型用户，提供多后端的统一编译能力；对于下游芯片厂商，提供 Triton 生态接入范例。
 
 ## 新特性
+* 2025/11/26 添加 FlagTree 后端特化统一设计文档 [FlagTree_Backend_Specialization](reports/decoupling/)。
 * 2025/09/30 在 GPGPU 上支持编译指导 shared memory。
 * 2025/09/29 SDK 存储迁移至金山云，大幅提升下载稳定性。
 * 2025/09/25 支持编译指导 ascend 的后端编译能力。

include/triton/Analysis/Allocation.h

@@ -9,20 +9,36 @@
 
 #include "triton/Dialect/Triton/IR/Dialect.h"
 #include "triton/Dialect/TritonGPU/IR/Dialect.h"
+#ifdef __NVIDIA__
 #include "triton/Dialect/TritonNvidiaGPU/IR/Dialect.h"
+#endif
 #include <atomic>
 #include <limits>
 
+#if __has_include("flagtree_spec.h")
+#include "flagtree_spec.h"
+#endif
+
 namespace mlir {
 
 namespace triton {
+
+#ifdef FLAGTREE_SPEC_Analysis_Allocation_getCvtOrder
+std::pair<SmallVector<unsigned>, SmallVector<unsigned>>
+getCvtOrder(Attribute srcLayout, Attribute dstLayout);
+#endif
+
 class AllocationAnalysis;
 
 SmallVector<unsigned>
 getScratchConfigForCvtLayout(triton::gpu::ConvertLayoutOp op, unsigned &inVec,
                              unsigned &outVec);
 SmallVector<unsigned> getRepShapeForCvtLayout(triton::gpu::ConvertLayoutOp op);
 
+#ifdef FLAGTREE_SPEC_Analysis_Allocation_AllocationAnalysis_getScratchValueSizeElems
+unsigned getScratchValueSizeElems(const SmallVector<unsigned> &smemShape);
+#endif
+
 } // namespace triton
 
 /// Modified from llvm-15.0: llvm/ADT/AddressRanges.h
@@ -175,6 +191,12 @@ class Allocation {
   /// BufferId -> Buffer
   using BufferSetT = std::map<BufferId, BufferT>;
 
+#ifdef FLAGTREE_SPEC_Analysis_Allocation_AllocationAnalysis_dump
+public:
+  friend class AllocationAnalysis;
+  static void dump(llvm::MapVector<BufferT *, Interval<size_t>> bufferRange);
+#endif
+
 private:
   template <BufferT::BufferKind Kind, typename KeyType, typename... Args>
   void addBuffer(KeyType &key, Args &&...args) {

include/triton/Analysis/AxisInfo.h

@@ -13,13 +13,18 @@
 #include <optional>
 #include <type_traits>
 
+#if __has_include("flagtree_spec.h")
+#include "flagtree_spec.h"
+#endif
+
 namespace mlir::triton {
 
 //===----------------------------------------------------------------------===//
 // AxisInfo
 //===----------------------------------------------------------------------===//
 
 /// This lattice value represents known information on the axes of a lattice.
+#ifndef FLAGTREE_SPEC_AxisInfo
 class AxisInfo {
 public:
   typedef SmallVector<int64_t> DimVectorT;
@@ -151,6 +156,7 @@ class AxisInfo {
   // The constant value of the lattice if we can infer it.
   std::optional<int64_t> constantValue;
 };
+#endif
 
 // Module level axis info analysis based on the call graph, assuming that we do
 // not have recursive functions.

include/triton/Analysis/Membar.h

@@ -6,6 +6,10 @@
 
 #include <set>
 
+#if __has_include("flagtree_spec.h")
+#include "flagtree_spec.h"
+#endif
+
 namespace mlir {
 
 class OpBuilder;
@@ -43,6 +47,16 @@ struct BlockInfo {
     syncWriteIntervals.clear();
   }
 
+#ifdef FLAGTREE_SPEC_BlockInfo_erase
+  // type: 0 all | 1 del W from other R |2 del R from other W
+  void erase(BlockInfo &other, int type = 0);
+#endif
+
+#ifdef FLAGTREE_SPEC_BlockInfo_printIntervals
+  // for debug
+  void printIntervals();
+#endif
+
   /// Compares two BlockInfo objects.
   bool operator==(const BlockInfo &other) const {
     return syncReadIntervals == other.syncReadIntervals &&

include/triton/Analysis/Utility.h

@@ -7,6 +7,10 @@
 #include "triton/Dialect/Triton/IR/Dialect.h"
 #include "triton/Dialect/TritonGPU/IR/Dialect.h"
 
+#if __has_include("flagtree_spec.h")
+#include "flagtree_spec.h"
+#endif
+
 namespace mlir {
 
 inline bool isZeroConst(Value v) {
@@ -194,6 +198,10 @@ bool isMmaToDotShortcut(RankedTensorType srcTy, RankedTensorType dstTy);
 
 bool isMmaToMmaShortcut(RankedTensorType srcTy, RankedTensorType dstTy);
 
+#ifdef FLAGTREE_SPEC_Analysis_Utility_isMmaToMmaShortcut
+bool isMmaToMmaShortcut(Attribute srcEncoding, Attribute dstEncoding);
+#endif
+
 // Return true if the src and dst layout match.
 bool matchMmaV3AndDotOperandLayout(RankedTensorType srcTy,
                                    RankedTensorType dstTy);
@@ -210,10 +218,35 @@ bool shouldUseDistSmem(Attribute srcLayout, Attribute dstLayout);
 SetVector<Operation *>
 multiRootTopologicalSort(const SetVector<Operation *> &toSort);
 
+#ifdef FLAGTREE_SPEC_Utility_isMmaToDotSlowShortcut
+bool isMmaToDotSlowShortcut(RankedTensorType &srcTy, RankedTensorType &dstTy);
+#endif
+
+#ifdef FLAGTREE_SPEC_Utility_getBackwardSliceCorex
+/// This function dones't use assertion check.
+void getBackwardSliceCorex(Operation *op, SetVector<Operation *> *backwardSlice,
+                           TransitiveFilter filter = nullptr,
+                           bool omitBlockArguments = false);
+#endif
+
+#ifdef FLAGTREE_SPEC_Utility_getBackwardSliceImplCorex
+void getBackwardSliceImplCorex(Operation *op,
+                               SetVector<Operation *> *backwardSlice,
+                               TransitiveFilter filter,
+                               bool omitBlockArguments = false);
+
+#endif
+
 /// This uses the toplogicalSort above
 SetVector<Operation *>
 multiRootGetSlice(Operation *op, TransitiveFilter backwardFilter = nullptr,
+#ifndef FLAGTREE_SPEC_Utility_multiRootGetSlice_ARG
                   TransitiveFilter forwardFilter = nullptr);
+#else
+                  TransitiveFilter forwardFilter = nullptr,
+                  FLAGTREE_SPEC_Utility_multiRootGetSlice_ARG
+                      omitBlockArguments = true);
+#endif
 
 /// Create a basic DataFlowSolver with constant and dead code analysis included.
 std::unique_ptr<DataFlowSolver> createDataFlowSolver();

include/triton/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVMBase.h

@@ -8,6 +8,10 @@
 #include "triton/Conversion/TritonGPUToLLVM/PatternTritonGPUOpToLLVM.h"
 #include "triton/Conversion/TritonGPUToLLVM/Utility.h"
 
+#if __has_include("flagtree_spec.h")
+#include "flagtree_spec.h"
+#endif
+
 using namespace mlir;
 using namespace mlir::triton;
 
@@ -28,6 +32,15 @@ SmallVector<Value> packI32(const SmallVector<Value> &inValues, Type srcTy,
 
 Type getElementType(Value value);
 
+#ifdef FLAGTREE_SPEC_ElementwiseOpConversionBase_maybeDeduplicate
+bool maybeDeduplicate_baseEncoding(Attribute baseEncoding);
+#endif
+
+#ifdef FLAGTREE_SPEC_ElementwiseOpConversionBase_matchAndRewrite
+void matchAndRewrite_elemTy(const mlir::TypeConverter *typeConverter,
+                            mlir::Type &elemTy, const mlir::Type &resultTy);
+#endif
+
 class MultipleOperandsRange
     : public iterator_range<SmallVector<SmallVector<Value>>::iterator> {
   using ContainerT = SmallVector<SmallVector<Value>>;
@@ -102,6 +115,10 @@ class ElementwiseOpConversionBase : public ConvertOpToLLVMPattern<SourceOp> {
       // test_core::test_fp8_dot_acc
       return resultVals;
     }
+#ifdef FLAGTREE_SPEC_ElementwiseOpConversionBase_maybeDeduplicate
+    if (maybeDeduplicate_baseEncoding(baseEncoding))
+      return resultVals;
+#endif
 
     SmallVector<unsigned> elemsPerThread = getElemsPerThread(rtType);
     int rank = elemsPerThread.size();
@@ -182,6 +199,9 @@ class ElementwiseOpConversionBase : public ConvertOpToLLVMPattern<SourceOp> {
     // element type
     auto resultElementTy = getElementTypeOrSelf(resultTy);
     Type elemTy = this->getTypeConverter()->convertType(resultElementTy);
+#ifdef FLAGTREE_SPEC_ElementwiseOpConversionBase_matchAndRewrite
+    matchAndRewrite_elemTy(this->getTypeConverter(), elemTy, resultTy);
+#endif
     SmallVector<SmallVector<Value>> allOperands;
     for (auto operand : adaptor.getOperands()) {
       auto argTy = op->getOperand(0).getType();

include/triton/Conversion/TritonGPUToLLVM/TargetInfoBase.h

@@ -3,6 +3,10 @@
 
 #include "triton/Conversion/MLIRTypes.h"
 
+#if __has_include("flagtree_spec.h")
+#include "flagtree_spec.h"
+#endif
+
 namespace mlir::triton {
 class TargetInfoBase {
 public:
@@ -13,11 +17,18 @@ class TargetInfoBase {
   virtual Value ballot(ConversionPatternRewriter &rewriter, Location loc,
                        Type type, Value cmp) const = 0;
 
+#ifdef FLAGTREE_SPEC_TargetInfoBase_function
+  virtual Value storeShared(ConversionPatternRewriter &rewriter, Location loc,
+                            Value ptr, Value val, Value pred) const = 0;
+  virtual Value loadShared(ConversionPatternRewriter &rewriter, Location loc,
+                           Value ptr, Type elemTy, Value pred) const = 0;
+#else
   virtual void storeShared(ConversionPatternRewriter &rewriter, Location loc,
                            Value ptr, Value val, Value pred) const = 0;
   virtual Value loadShared(ConversionPatternRewriter &rewriter, Location loc,
                            const TypeConverter *converter, Value ptr,
                            Type elemTy, Value pred) const = 0;
+#endif
 
   virtual Value shuffleXor(ConversionPatternRewriter &rewriter, Location loc,
                            Value val, int i) const = 0;