11menu "Espressif Camera Sensors Configurations"
22 menu "Camera Sensor Configuration"
3- rsource "sensors/bf3901/Kconfig.bf3901"
4- rsource "sensors/bf3925/Kconfig.bf3925"
5- rsource "sensors/bf3a03/Kconfig.bf3a03"
6- rsource "sensors/gc0308/Kconfig.gc0308"
7- rsource "sensors/gc2145/Kconfig.gc2145"
8- rsource "sensors/ov2640/Kconfig.ov2640"
9- rsource "sensors/ov2710/Kconfig.ov2710"
10- rsource "sensors/ov5640/Kconfig.ov5640"
11- rsource "sensors/ov5645/Kconfig.ov5645"
12- rsource "sensors/ov5647/Kconfig.ov5647"
13- rsource "sensors/sc030iot/Kconfig.sc030iot"
14- rsource "sensors/sc035hgs/Kconfig.sc035hgs"
15- rsource "sensors/sc101iot/Kconfig.sc101iot"
16- rsource "sensors/sc202cs/Kconfig.sc202cs"
17- rsource "sensors/sc2336/Kconfig.sc2336"
3+ menu "Select and Set Camera Sensor"
4+ rsource "sensors/bf3901/Kconfig.bf3901"
5+ rsource "sensors/bf3925/Kconfig.bf3925"
6+ rsource "sensors/bf3a03/Kconfig.bf3a03"
7+ rsource "sensors/gc0308/Kconfig.gc0308"
8+ rsource "sensors/gc2145/Kconfig.gc2145"
9+ rsource "sensors/ov2640/Kconfig.ov2640"
10+ rsource "sensors/ov2710/Kconfig.ov2710"
11+ rsource "sensors/ov5640/Kconfig.ov5640"
12+ rsource "sensors/ov5645/Kconfig.ov5645"
13+ rsource "sensors/ov5647/Kconfig.ov5647"
14+ rsource "sensors/sc030iot/Kconfig.sc030iot"
15+ rsource "sensors/sc035hgs/Kconfig.sc035hgs"
16+ rsource "sensors/sc101iot/Kconfig.sc101iot"
17+ rsource "sensors/sc202cs/Kconfig.sc202cs"
18+ rsource "sensors/sc2336/Kconfig.sc2336"
19+ endmenu
1820
1921 config CAMERA_SENSOR_SWAP_PIXEL_BYTE_ORDER
20- bool "Swap Pixel Byte Order "
22+ bool "Enable pixel byte order swapping "
2123 default y if IDF_TARGET_ESP32P4
2224 default n if IDF_TARGET_ESP32S3
2325 depends on CAMERA_OV2640 || CAMERA_BF3901
2426 help
25- If enabled, the pixel byte order will be swapped, for example:
27+ Enable pixel byte order swapping to match display or processing requirements.
2628
27- Original RGB565 byte order:
28- 0x00 0x01 0x02 0x03 0x04 0x05
29- B G R B G R B G R
29+ This feature exchanges the byte order of pixel data, which is useful when interfacing
30+ with different display controllers or image processing pipelines that expect specific
31+ byte ordering.
3032
31- Swapped RGB565 byte order:
32- 0x00 0x01 0x02 0x03 0x04 0x05
33- R G B R G B R G B
33+ Supported transformations:
3434
35- Original YUYV byte order :
36- 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
37- Y U Y V Y U Y V
35+ RGB565 format :
36+ Original: [R₁G₁B₁][R₂G₂B₂] → Swapped: [B₁G₁R₁][B₂G₂R₂]
37+ Byte sequence: 0xRG 0xBR 0xGB → 0xBG 0xRB 0xGR
3838
39- Swapped YUYV byte order :
40- 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
41- U Y V Y U Y V Y
39+ YUYV format :
40+ Original: [Y₁U₁Y₂V₁] → Swapped: [U₁Y₁V₁Y₂]
41+ Byte sequence: Y U Y V → U Y V Y
4242
43- Please note that this option is only valid for OV2640 and BF3901.
43+ Platform compatibility:
44+ - ESP32-P4: Default enabled
45+ - ESP32-S3: Default disabled
4446
45- If you want to swap the pixel byte order of other sensors,
46- please use ESP_VIDEO_ENABLE_SWAP_BYTE. Only ESP32-P4 is supported;
47- other platforms are not supported.
47+ Note: This option only applies to OV2640 and BF3901 sensors.
48+ For other sensors, use ESP_VIDEO_ENABLE_SWAP_BYTE (ESP32-P4 only).
4849 endmenu
49-
50- menu "Camera XCLK generator Configuration"
50+
51+ menu "Camera XCLK Generator Configuration"
5152 config CAMERA_XCLK_USE_LEDC
52- bool "XCLK generated by LEDC"
53+ bool "Generate XCLK using LEDC"
5354 default n if IDF_TARGET_ESP32P4
5455 default y
5556 help
56- If enabled, XCLK can be generated from LEDC.
57-
57+ Use the LED Control (LEDC) peripheral to generate the external clock (XCLK) signal
58+ for camera sensors.
59+
60+ The LEDC peripheral provides a flexible PWM-based clock generation method that is
61+ compatible with most ESP32 variants. It offers good frequency accuracy and is
62+ suitable for most camera sensor applications.
63+
5864 config CAMERA_XCLK_USE_ESP_CLOCK_ROUTER
59- bool "XCLK generated by ESP clock router"
65+ bool "Generate XCLK using ESP clock router"
6066 depends on IDF_TARGET_ESP32P4
6167 default y
6268 help
63- If enabled, XCLK can be generated from SoC's supported root clocks. Please refer to SoC's supported root clocks at:
64- `https://docs.espressif.com/projects/esp-idf/en/latest/esp32p4/api-reference/peripherals/clk_tree.html`
69+ Use the ESP32-P4's dedicated clock router to generate the external clock (XCLK)
70+ signal for camera sensors.
71+
72+ The clock router provides high-precision clock generation directly from the SoC's
73+ root clock sources, offering superior frequency stability and accuracy compared
74+ to LEDC-based generation.
75+
76+ For detailed clock tree information, refer to:
77+ https://docs.espressif.com/projects/esp-idf/en/latest/esp32p4/api-reference/peripherals/clk_tree.html
78+
79+ Recommended for: High-performance camera applications requiring precise timing.
6580 endmenu
6681
67- menu "Camera Motor Configuration"
82+ menu "Camera Motor Control Configuration"
6883 rsource "motors/dw9714/Kconfig.dw9714"
6984
7085 config CAMERA_MOTOR_DEVICE_USED
71- bool
86+ bool
7287 default n
7388 help
74- This option indicates whether any camera motor driver is enabled in the configuration.
75- It is automatically set when any of the motor drivers are enabled.
89+ Internal configuration flag indicating whether any camera motor driver is enabled.
90+
91+ This flag is automatically set when any motor driver (such as autofocus motors,
92+ zoom motors, or iris control motors) is enabled in the configuration. It is used
93+ internally by the build system to include necessary motor control libraries and
94+ initialization code.
95+
96+ Do not modify this setting manually - it is managed automatically based on
97+ your motor driver selections.
7698
7799 endmenu
78100
79- menu "Camera Controller SPI Configuration"
101+ menu "Camera SPI Controller Configuration"
80102 config CAM_CTLR_SPI_ISR_CACHE_SAFE
81- bool "Camera Controller SPI ISR Cache-Safe "
103+ bool "Enable cache-safe SPI interrupt handling "
82104 default y
83105 select SPI_SLAVE_ISR_IN_IRAM
84106 help
85- Ensure the camera controller SPI ISR is Cache-Safe. When enabled, the ISR handler
86- will be available when the cache is disabled.
107+ Ensure camera controller SPI interrupt service routine (ISR) remains accessible
108+ when cache is disabled.
109+
110+ When enabled, the SPI ISR code is placed in internal RAM (IRAM), allowing it to
111+ execute even when external flash cache is temporarily disabled during operations
112+ like flash writes, OTA updates, or power management transitions.
113+
114+ Benefits:
115+ - Prevents SPI communication interruptions during cache-disabled periods
116+ - Ensures reliable camera data transfer during system operations
117+ - Reduces latency in time-critical camera control scenarios
118+
119+ Trade-offs:
120+ - Uses additional IRAM memory
121+ - Slightly increases firmware size
122+
123+ Recommended: Enable for production applications requiring reliable camera operation
124+ during all system states.
125+
126+ Note: This automatically enables SPI_SLAVE_ISR_IN_IRAM for the SPI peripheral.
87127 endmenu
88- endmenu
128+ endmenu
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