Kunteng?

[aalm]

Wrote something that might be seen as an improvement for tsdz2 also.

Gave that a shot, and now have things running nicely. Setting software priorities like this:

	/* in hw priority order - code from main() is always lowest level 0 when irqs enabled */
	ITC_SetSoftwarePriority(ITC_IRQ_PORTA, ITC_PRIORITYLEVEL_1);			/* low */
	ITC_SetSoftwarePriority(ITC_IRQ_PORTD, ITC_PRIORITYLEVEL_1);			/* low */
	ITC_SetSoftwarePriority(ITC_IRQ_TIM1_CAPCOM, ITC_PRIORITYLEVEL_2);	/* mid */
	ITC_SetSoftwarePriority(ITC_IRQ_TIM3_OVF, ITC_PRIORITYLEVEL_1);			/* low */
	ITC_SetSoftwarePriority(ITC_IRQ_UART2_TX, ITC_PRIORITYLEVEL_1);			/* low */
	ITC_SetSoftwarePriority(ITC_IRQ_UART2_RX, ITC_PRIORITYLEVEL_1);			/* low */
	ITC_SetSoftwarePriority(ITC_IRQ_ADC1, ITC_PRIORITYLEVEL_3);	/* high */
	ITC_SetSoftwarePriority(ITC_IRQ_TIM4_OVF, ITC_PRIORITYLEVEL_1);			/* low */

is what allows to run start of timer1 irq handler like this:

void
isr_timer1_cmp(void) __interrupt(ITC_IRQ_TIM1_CAPCOM)
{
	GPIO_WriteHigh(DBG_P0_IOT);
	/* grab the latest continuous current conversion value */
	volatile uint8_t hi = ADC1->DRH;
	volatile uint8_t lo = ADC1->DRL;
	adc_battery_current = (uint16_t)(hi << 2) | lo;
	adc_battery_current -= adc_battery_zero_current;

	/* will trigger conversion for throttle, and return to continuous for current after that */
	adc_trigger_eoc(ADC1_ALIGN_LEFT, ADC1_CHANNEL_BATTERY_VOLTAGE);

	switch (control_state) {
	case CONTROL_STATE_DISABLE:

and adc irq then does what the comment says, after reading battery voltage it will start conversion
on throttle before going back to continous for current, which is the shorter pulse seen below:

So, from start to finish the adc operations take about 14us of the time, AND it uses some of that
to work on rest of the stuff it has to do anyway - using the scanning w/adc includes time spent on
useless input, and so it happens somewhere most of the time, because it is relatively low on priorities,
which doesn't result in as consistent sampling as far as i can tell(possible pauses from level 0 and
other irqs do mess up with that).

Any thoughts on this ?

[aalm]

Oh, my example does the current reading in left alignment, but that's nothing to adapt back
to a separate _ovf-variable.

[aalm]

If there's anyone interested&able to test i could make a branch(&binary if necessary) for this.

I'm guessing "hand adjusted" OC4 timing might need to be readjusted, but atm. i don't have
the tools/hardware necessary for doing that w/any accuracy.

[Larswagner1987]

I can only test for Bbshd, if it is for the engine then I am happy to test it.

[aalm]

This is just for the stm8(TSDZ2). So doesn't affect BBS's in any way, but thank you for the offer.

[aalm]

So, from start to finish the adc operations take about 14us of the time, AND it uses some of that to work on rest of the stuff it has to do anyway - using the scanning w/adc includes time spent on useless input, and so it happens somewhere most of the time, because it is relatively low on priorities, which doesn't result in as consistent sampling as far as i can tell(possible pauses from level 0 and other irqs do mess up with that).

To clarify what i wrote above a bit, with "somewhere" i meant about when the code in level zero
will receive it - those values are of course sampled at "known offset"(but variable!) to timer1 irq.
So that gives two variable delays to the "when".

[Larswagner1987]

no problem Yahoo Mail: Suchen, organisieren, erobern Am Fr., Aug. 1, 2025 at 15:36 schrieb ***@***.***>: This is just for the stm8(TSDZ2). So doesn't affect BBS's in any way, but thank you for the offer. — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you commented.Message ID: ***@***.***>

[aalm]

Just noticed; the code for tsdz2 does atm. read the result for adc_battery_current in wrong order.

RM0016 for stm8 page 445:

Bit 3 ALIGN: Data alignment
This bit is set and cleared by software.
0: Left alignment (the eight MSB bits are written in the ADC_DRH register then the remaining LSB
bits are written in the ADC_DRL register). The reading order should be MSB first and then LSB.
1: Right alignment (eight LSB bits are written in the ADC_DRL register then the remaining MSB bits
are written in the ADC_DH register). The reading order should be LSB first and then MSB.
Note: The ALIGN bit influences the ADC_DRH/ADC_DRL register reading order and not the reading
order of the buffer registers.

What most likely that won't affect anything, as it's not used as a whole, so this is not a bug report.
Just an observation.

[aalm]

Fwiw., i got bbs-fw working on kunteng controller*, but it is still throttle-only(i got no PAS-hw).
Since the usual PAS sensor sold with these is totally different from bafang/tsdz2, i just removed the code
for that to use the pin as debug output, but there's a free timer that could be used to capture input from
PAS, allowing simpler/better PAS handling than what i've seen other opensource projects use(counting
IRQs+pin high/low from level 0-code and what not).

Currently waiting for a scope i bought to arrive, so i could try to measure which way to adjust the OC4
"hand adjusted" timing.

*) KT36/48SVPRD-HRDF02L (6fet version: rated current 10A, max current 20A+/-1A) from pswpower.com.
Using it w/mxus XF15R-48's bought from the same place. My first use-case is a trike w/no pedals, to keep
it "legal" in .fi w/throttle(also requires <=25km/h speed limit for standard mode).