patents.htm

<h3>This document has been edited.

<h1 align="center">ATTACHMENT 1
<br>SCHEDULE OF PATENTS</h1><ul>
<li>US 5,440,749 Hi Perf, Lo cost Micro Arch - issued Aug 1995
<br>High-performance, low-cost micro-processor architecture
<li>US 5,530,890 Hi Perf, Lo cost Micro Arch - Jun 95
<li>US 5,659,703 Micro Sys with Hierarchical stack - Aug 97
<li>US 5,784,584 Multiple Instructions within Groups - Jul 98
<li>US 5,809,336 Hi Perf Variable Speed Sys Clock - Sep 98
<li>US 5,604,915 Load Dependent Bus Timing - Feb 97
<li>US 6,598,148 Hi Perf Variable Speed Sys Clock
<li>DE 69033568.7 Hi Perf, Lo Cost Micro - Jun 00
<li>DE 69033568T2 Preisguenstiger Hochleistungsmikro - Mar 01
<li>DE 69033568C0 Preisguenstiger Hochleistungsmikro - Jul 00
<li>EP 0786730 Hi Perf, Lo Cost Micro - Jun 00
<li>EP 786730A1 Hi Perf, Lo Cost Micro - Jul 97
<li>EP 497772A4 Hi Perf, Lo Cost Micro - Aug 93
<li>EP 497772A1 Hi Perf, Lo Cost Micro - Aug 92
<li>EP 0870226
<li>FR 0786730 Hi Perf, Lo Cost Micro - Jul 00
<li>WO 9715001 RISC Microprocessor Arch
<li>WO 9102311A3 Hi Perf, Lo Cost Micro - Mar 91
<li>WO 9102311A1 Hi Perf, Lo Cost Micro - Feb 91
<li>JP 5502125T2 - Apr 93
<li>JP 2966085B2 - Oct 99
<li>AU 6067290A1 Hi Perf, Lo Cost Micro - Mar 91</ul>