Add support for RTL8211

Author: scaprile

mongoose.c

@@ -23466,6 +23466,8 @@ enum {
   MG_PHY_LAN87x_REG_SCSR = 31,
   MG_PHY_RTL8201_REG_RMSR = 16,  // in page 7
   MG_PHY_RTL8201_REG_PAGESEL = 31,
+  MG_PHY_RTL8211_REG_PHYSR = 26,  // in page a43
+  MG_PHY_RTL8211_REG_PAGESEL = 31,
   MG_PHY_ICS189432_REG_POLL = 17
 };
 
@@ -23537,14 +23539,14 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
                      (uint16_t) (MG_BIT(15) | MG_BIT(8) | MG_BIT(7)));
     } else if (id1 == MG_PHY_LAN87x) {
       // nothing to do
-    } else if (id1 == MG_PHY_RTL8201) {
+    } else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8201) {
       // assume PHY has been hardware strapped properly
 #if 0
       phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 7);  // Select page 7
       phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_RMSR, 0x1ffa);
       phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 0);  // Select page 0
 #endif
-    } else if (id1 == MG_PHY_RTL8211) {
+    } else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8211) {
       // assume PHY has been hardware strapped properly
     }
   }
@@ -23587,11 +23589,18 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
       *speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
     } else if (id1 == MG_PHY_RTL82x) {
       uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
-      uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
-      *full_duplex = bcr & MG_BIT(8);
       if (id2 == MG_PHY_RTL8211) {
-        *speed = (bcr & MG_BIT(6)) ? MG_PHY_SPEED_1000M : (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
+        uint16_t physr;
+        phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0xa43);
+        physr = phy->read_reg(phy_addr, MG_PHY_RTL8211_REG_PHYSR);
+        phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0);
+        *full_duplex = physr & MG_BIT(3);
+        *speed = (physr & MG_BIT(5))   ? MG_PHY_SPEED_1000M
+                 : (physr & MG_BIT(4)) ? MG_PHY_SPEED_100M
+                                       : MG_PHY_SPEED_10M;
       } else {
+        uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
+        *full_duplex = bcr & MG_BIT(8);
         *speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
       }
     } else if (id1 == MG_PHY_ICS1894x) {

src/drivers/phy.c

@@ -28,6 +28,8 @@ enum {
   MG_PHY_LAN87x_REG_SCSR = 31,
   MG_PHY_RTL8201_REG_RMSR = 16,  // in page 7
   MG_PHY_RTL8201_REG_PAGESEL = 31,
+  MG_PHY_RTL8211_REG_PHYSR = 26,  // in page a43
+  MG_PHY_RTL8211_REG_PAGESEL = 31,
   MG_PHY_ICS189432_REG_POLL = 17
 };
 
@@ -99,14 +101,14 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
                      (uint16_t) (MG_BIT(15) | MG_BIT(8) | MG_BIT(7)));
     } else if (id1 == MG_PHY_LAN87x) {
       // nothing to do
-    } else if (id1 == MG_PHY_RTL8201) {
+    } else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8201) {
       // assume PHY has been hardware strapped properly
 #if 0
       phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 7);  // Select page 7
       phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_RMSR, 0x1ffa);
       phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 0);  // Select page 0
 #endif
-    } else if (id1 == MG_PHY_RTL8211) {
+    } else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8211) {
       // assume PHY has been hardware strapped properly
     }
   }
@@ -149,11 +151,18 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
       *speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
     } else if (id1 == MG_PHY_RTL82x) {
       uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
-      uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
-      *full_duplex = bcr & MG_BIT(8);
       if (id2 == MG_PHY_RTL8211) {
-        *speed = (bcr & MG_BIT(6)) ? MG_PHY_SPEED_1000M : (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
+        uint16_t physr;
+        phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0xa43);
+        physr = phy->read_reg(phy_addr, MG_PHY_RTL8211_REG_PHYSR);
+        phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0);
+        *full_duplex = physr & MG_BIT(3);
+        *speed = (physr & MG_BIT(5))   ? MG_PHY_SPEED_1000M
+                 : (physr & MG_BIT(4)) ? MG_PHY_SPEED_100M
+                                       : MG_PHY_SPEED_10M;
       } else {
+        uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
+        *full_duplex = bcr & MG_BIT(8);
         *speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
       }
     } else if (id1 == MG_PHY_ICS1894x) {