Feature: Restore lost JTAG-DP state across resets

src/platforms/hosted/remote/protocol_v4.c

@@ -103,6 +103,7 @@ bool remote_v4_adiv5_init(adiv5_debug_port_s *const dp)
 	dp->ap_write = remote_v4_adiv5_ap_write;
 	dp->mem_read = remote_v4_adiv5_mem_read_bytes;
 	dp->mem_write = remote_v4_adiv5_mem_write_bytes;
+	dp->ensure_idle = remote_v4_jtag_ensure_idle;
 	return true;
 }
 
@@ -133,3 +134,18 @@ bool remote_v4_riscv_jtag_init(riscv_dmi_s *const dmi)
 	dmi->write = remote_v4_riscv_jtag_dmi_write;
 	return true;
 }
+
+void remote_v4_jtag_ensure_idle(adiv5_debug_port_s *dp)
+{
+	/* Ask remote_dp !JI# to set IR cache to BYPASS (because a reset happened) */
+	platform_buffer_write(REMOTE_JTAG_ENSURE_IDLE_STR, sizeof(REMOTE_JTAG_ENSURE_IDLE_STR));
+	char buffer[REMOTE_MAX_MSG_SIZE];
+	/* Read back the answer and check for errors */
+	const int length = platform_buffer_read(buffer, REMOTE_MAX_MSG_SIZE);
+	if (length < 1 || buffer[0U] != REMOTE_RESP_OK) {
+		DEBUG_ERROR("%s failed, error %s\n", __func__, length ? buffer + 1 : "with communication");
+		return;
+	}
+	jtag_devs[dp->dev_index].current_ir = 0xffU;
+	jtagtap_return_idle(1);
+}

src/platforms/hosted/remote/protocol_v4.h

@@ -43,5 +43,6 @@ bool remote_v4_init(void);
 bool remote_v4_adiv5_init(adiv5_debug_port_s *dp);
 bool remote_v4_adiv6_init(adiv5_debug_port_s *dp);
 bool remote_v4_riscv_jtag_init(riscv_dmi_s *dmi);
+void remote_v4_jtag_ensure_idle(adiv5_debug_port_s *dp);
 
 #endif /*PLATFORMS_HOSTED_REMOTE_PROTOCOL_V4_H*/

src/platforms/hosted/remote/protocol_v4_defs.h

@@ -101,6 +101,13 @@
 		REMOTE_SOM, REMOTE_ADIV5_PACKET, REMOTE_DP_TARGETSEL, REMOTE_ADIV5_DATA, REMOTE_EOM, 0 \
 	}
 
+#define REMOTE_JTAG_ENSURE_IDLE 'I'
+#define REMOTE_JTAG_ENSURE_IDLE_STR                                            \
+	(char[])                                                                   \
+	{                                                                          \
+		REMOTE_SOM, REMOTE_JTAG_PACKET, REMOTE_JTAG_ENSURE_IDLE, REMOTE_EOM, 0 \
+	}
+
 /* ADIv6 acceleration protocol elements */
 #define REMOTE_ADIV6_PACKET '6'
 

src/remote.c

@@ -192,6 +192,7 @@ static void remote_packet_process_jtag(const char *const packet, const size_t pa
 		remote_dp.error = adiv5_jtag_clear_error;
 		remote_dp.low_access = adiv5_jtag_raw_access;
 		remote_dp.abort = adiv5_jtag_abort;
+		remote_dp.ensure_idle = adiv5_jtag_ensure_idle;
 		jtagtap_init();
 		remote_respond(REMOTE_RESP_OK, 0);
 		break;
@@ -249,6 +250,11 @@ static void remote_packet_process_jtag(const char *const packet, const size_t pa
 		break;
 	}
 
+	case REMOTE_JTAG_ENSURE_IDLE: /* JI = re-cycle IR after indirect resets */
+		remote_dp.ensure_idle(&remote_dp);
+		remote_respond(REMOTE_RESP_OK, 0);
+		break;
+
 	default:
 		remote_respond(REMOTE_RESP_ERR, REMOTE_ERROR_UNRECOGNISED);
 		break;

src/remote.h

@@ -253,6 +253,8 @@
 #define REMOTE_ACCEL_RISCV     (1U << 2U)
 #define REMOTE_ACCEL_ADIV6     (1U << 3U)
 
+#define REMOTE_JTAG_ENSURE_IDLE 'I'
+
 /* ADIv5 accleration protocol elements */
 #define REMOTE_ADIV5_PACKET     'A'
 #define REMOTE_DP_READ          'd'

src/target/adiv5.h

@@ -294,5 +294,6 @@ uint32_t adiv5_jtag_read(adiv5_debug_port_s *dp, uint16_t addr);
 uint32_t adiv5_jtag_raw_access(adiv5_debug_port_s *dp, uint8_t rnw, uint16_t addr, uint32_t value);
 uint32_t adiv5_jtag_clear_error(adiv5_debug_port_s *dp, bool protocol_recovery);
 void adiv5_jtag_abort(adiv5_debug_port_s *dp, uint32_t abort);
+void adiv5_jtag_ensure_idle(adiv5_debug_port_s *dp);
 
 #endif /* TARGET_ADIV5_H */

src/target/adiv5_internal.h

@@ -203,6 +203,7 @@ struct adiv5_debug_port {
 	uint32_t (*error)(adiv5_debug_port_s *dp, bool protocol_recovery);
 	uint32_t (*low_access)(adiv5_debug_port_s *dp, uint8_t RnW, uint16_t addr, uint32_t value);
 	void (*abort)(adiv5_debug_port_s *dp, uint32_t abort);
+	void (*ensure_idle)(adiv5_debug_port_s *dp);
 
 #if CONFIG_BMDA == 1
 	void (*ap_regs_read)(adiv5_access_port_s *ap, void *data);

src/target/adiv5_jtag.c

@@ -55,6 +55,7 @@ void adiv5_jtag_dp_handler(const uint8_t dev_index)
 	dp->low_access = adiv5_jtag_raw_access;
 	dp->error = adiv5_jtag_clear_error;
 	dp->abort = adiv5_jtag_abort;
+	dp->ensure_idle = adiv5_jtag_ensure_idle;
 #if CONFIG_BMDA == 1
 	bmda_jtag_dp_init(dp);
 #endif
@@ -175,3 +176,14 @@ void adiv5_jtag_abort(adiv5_debug_port_s *dp, uint32_t abort)
 	jtag_dev_write_ir(dp->dev_index, IR_ABORT);
 	jtag_dev_shift_dr(dp->dev_index, NULL, (const uint8_t *)&request, 35);
 }
+
+void adiv5_jtag_ensure_idle(adiv5_debug_port_s *dp)
+{
+	/*
+	 * On devices where nRST pulls TRST, the JTAG-DP's IR is reset
+	 * from DPACC/APACC to IDCODE. We want BYPASS in case of daisy-chaining.
+	 */
+	jtag_devs[dp->dev_index].current_ir = 0xffU;
+	/* Go from TLR to RTI. */
+	jtagtap_return_idle(1);
+}

src/target/cortexm.c

@@ -784,6 +784,11 @@ static void cortexm_reset(target_s *const target)
 		platform_delay(10);
 	}
 
+	adiv5_access_port_s *ap = cortex_ap(target);
+	adiv5_debug_port_s *dp = ap->dp;
+	if (dp->ensure_idle)
+		dp->ensure_idle(dp);
+
 	/* Check if the reset succeeded */
 	const uint32_t status = target_mem32_read32(target, CORTEXM_DHCSR);
 	if (!(status & CORTEXM_DHCSR_S_RESET_ST)) {
@@ -792,6 +797,9 @@ static void cortexm_reset(target_s *const target)
 		 * Trigger reset by AIRCR.
 		 */
 		target_mem32_write32(target, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
+		platform_delay(10);
+		if (dp->ensure_idle)
+			dp->ensure_idle(dp);
 	}
 
 	/* If target needs to do something extra (see Atmel SAM4L for example) */