diff --git a/cross-file/bluepill.ini b/cross-file/bluepill.ini index 50028721002..11937ff2664 100644 --- a/cross-file/bluepill.ini +++ b/cross-file/bluepill.ini @@ -19,6 +19,6 @@ endian = 'little' [project options] probe = 'bluepill' -targets = 'cortexm,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = true diff --git a/cross-file/f072.ini b/cross-file/f072.ini index 2382d205205..6429b018307 100644 --- a/cross-file/f072.ini +++ b/cross-file/f072.ini @@ -19,6 +19,6 @@ endian = 'little' [project options] probe = 'f072' -targets = 'cortexm,riscv32,riscv64,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,riscv32,riscv64,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = false diff --git a/cross-file/native.ini b/cross-file/native.ini index 2aaae354ad4..c92ee9c66a7 100644 --- a/cross-file/native.ini +++ b/cross-file/native.ini @@ -22,6 +22,6 @@ endian = 'little' [project options] probe = 'native' -targets = 'cortexm,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = true diff --git a/cross-file/swlink.ini b/cross-file/swlink.ini index 3a744b7675f..099c761dcff 100644 --- a/cross-file/swlink.ini +++ b/cross-file/swlink.ini @@ -19,6 +19,6 @@ endian = 'little' [project options] probe = 'swlink' -targets = 'cortexm,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = false diff --git a/meson_options.txt b/meson_options.txt index 9129524f380..9e848e0069e 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -37,19 +37,25 @@ option( 'ch579', 'efm', 'gd32', + 'gd32_rv', 'hc32', 'lpc', 'mm32', 'nrf', 'nxp', 'puya', + 'renesas_ra', + 'renesas_rz', 'renesas', 'rp', 'sam', + 'stm32f1', + 'stm32f4', 'stm', 'ti', 'xilinx' ], + value: [], description: 'Enabled debug targets' ) option( diff --git a/src/meson.build b/src/meson.build index bb71a4b7410..5afcba3d162 100644 --- a/src/meson.build +++ b/src/meson.build @@ -93,6 +93,12 @@ if advertise_noackmode libbmd_core_args += ['-DADVERTISE_NOACKMODE=1'] endif +# Check if we should enable the RISC-V Debug remote protocol acceleration and do so if required +enable_riscv_accel = get_option('enable_riscv_accel') +if enable_riscv_accel + bmd_core_args += ['-DCONFIG_RISCV_ACCEL=1'] +endif + # Get BMD targets dependency subdir('target') @@ -126,6 +132,7 @@ summary( 'RTT support': rtt_support, 'RVSWD support': rvswd_support, 'Advertise QStartNoAckMode': advertise_noackmode, + 'RISC-V acceleration': enable_riscv_accel, }, bool_yn: true, section: 'Black Magic Debug', diff --git a/src/target/meson.build b/src/target/meson.build index f04bd7f1226..3048fb1a483 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -29,10 +29,10 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -target_common_includes = include_directories('.') - subdir('flashstub') +target_common_includes = include_directories('.') + target_common_sources = files( 'adi.c', 'adiv5.c', @@ -58,95 +58,44 @@ if get_option('no_own_ll') ) endif -if is_firmware_build - enabled_targets = get_option('targets') - - # Check that at least one target is enabled - assert( - enabled_targets.length() > 0, - '''No debug targets enabled, please enable at least one target to build. - See the 'targets' option for a list of available targets. - ''', - ) - - # Build a dictionary mapping all target short names to proper textual naming - target_names = { - 'cortexar': 'Cortex-A/R support', - 'cortexm': 'Cortex-M support', - 'riscv32': 'RISC-V 32-bit support', - 'riscv64': 'RISC-V 64-bit support', - 'at32f4': 'Arterytek parts', - 'apollo3': 'Ambiq Apollo3 parts', - 'ch32': 'WinChipHead CH32 ARM Cortex parts', - 'ch32v': 'WinChipHead CH32 RISC-V parts', - 'ch579': 'WinChipHead CH579 parts', - 'efm': 'Energy Micro parts', - 'gd32': 'GigaDevice parts', - 'hc32': 'HC32 parts', - 'lpc': 'LPC series parts', - 'mm32': 'MindMotion parts', - 'nrf': 'nRF series parts', - 'nxp': 'Kinetis series parts', - 'puya': 'Puya PY32 series parts', - 'renesas': 'Renesas parts', - 'rp': 'Raspberry Pi MCUs (RP2040, RP2350)', - 'sam': 'ATSAM series parts', - 'stm': 'STM32 (and clones) parts', - 'ti': 'Texas Instruments parts', - 'xilinx': 'Xilinx parts', - } - - # Check to see if the set of enabled targets is all of them and the - # firmware is to be built for a STM32F1 based probe (requires a restriction) - if probe in ['bluepill', 'native', 'stlink', 'swlink'] and enabled_targets.length() == target_names.keys().length() - warning('Disabling some targets as your build will not fit the target probe otherwise') - enabled_targets = ['cortexm', 'lpc', 'nrf', 'nxp', 'renesas', 'rp', 'sam', 'stm', 'ti'] - elif probe in ['f072'] and enabled_targets.length() == target_names.keys().length() - warning('Disabling some targets as your build will not fit the target probe otherwise') - enabled_targets = [ - 'cortexm', - 'riscv32', - 'riscv64', - 'lpc', - 'nrf', - 'nxp', - 'renesas', - 'rp', - 'sam', - 'stm', - 'ti' - ] - endif -endif - # Conditional file compilation based on target selection # We declare a dependency for each target group with the source files required # these dependencies are then added to the BMD core, conditinal on the targets option # NOTE: sourceset module might be an alternative to this method (unexplored) -target_arm_coresight = declare_dependency( + +arm_coresight = declare_dependency( sources: files('arm_coresight_cti.c'), ) -target_cortex = declare_dependency( +cortex_common = declare_dependency( sources: files('cortex.c'), ) -target_cortexar = declare_dependency( - sources: files('cortexar.c'), - dependencies: target_cortex, - compile_args: ['-DCONFIG_CORTEXAR=1'], -) - -target_cortexm = declare_dependency( - sources: files('cortexm.c'), - dependencies: target_cortex, - compile_args: ['-DCONFIG_CORTEXM=1'], -) - -target_cortexa_armv8 = declare_dependency( - sources: files('cortexa_armv8.c'), - dependencies: [target_cortex, target_arm_coresight], -) +targets = { + 'cortexar': declare_dependency( + sources: files('cortexar.c'), + dependencies: cortex_common, + compile_args: ['-DCONFIG_CORTEXAR=1'], + variables: { + 'description': 'Cortex-A/R support' + } + ), + 'cortexm': declare_dependency( + sources: files('cortexm.c'), + dependencies: cortex_common, + compile_args: ['-DCONFIG_CORTEXM=1'], + variables: { + 'description': 'Cortex-M support' + } + ), + 'cortexa_armv8': declare_dependency( + sources: files('cortexa_armv8.c'), + dependencies: [cortex_common, arm_coresight], + variables: { + 'description': 'Cortex-A armv8 support' + } + ) +} riscv_jtag_dtm = declare_dependency( sources: files( @@ -154,7 +103,7 @@ riscv_jtag_dtm = declare_dependency( ), ) -target_riscv = declare_dependency( +riscv_common = declare_dependency( sources: files( 'riscv_debug.c', 'riscv_adi_dtm.c', @@ -163,296 +112,374 @@ target_riscv = declare_dependency( dependencies: riscv_jtag_dtm, ) -target_riscv32 = declare_dependency( - sources: files('riscv32.c'), - dependencies: target_riscv, -) - -target_riscv64 = declare_dependency( - sources: files('riscv64.c'), - dependencies: target_riscv, -) - -target_apollo3 = declare_dependency( - sources: files('apollo3.c'), - compile_args: ['-DCONFIG_APOLLO3=1'], - dependencies: target_cortexm, -) - -target_ch579 = declare_dependency( - sources: files('ch579.c'), - compile_args: ['-DCONFIG_CH579=1'], - dependencies: target_cortexm, -) - -target_efm = declare_dependency( - sources: files( - 'efm32.c' - ) + efm32_stub, - compile_args: ['-DCONFIG_EFM32=1'], - dependencies: target_cortexm, -) - -target_hc32 = declare_dependency( - sources: files('hc32l110.c'), - compile_args: ['-DCONFIG_HC32=1'], - dependencies: target_cortexm, -) - -target_lpc = declare_dependency( - sources: files( - 'lpc11xx.c', - 'lpc15xx.c', - 'lpc17xx.c', - 'lpc40xx.c', - 'lpc43xx.c', - 'lpc546xx.c', - 'lpc55xx.c', - 'lpc_common.c', - ), - compile_args: ['-DCONFIG_LPC=1'], - dependencies: target_cortexm, -) - -target_nrf = declare_dependency( - sources: files( - 'nrf51.c', - 'nrf54l.c', - 'nrf91.c', - ), - compile_args: ['-DCONFIG_NRF=1'], - dependencies: target_cortexm, -) - -target_nxp = declare_dependency( - sources: files( - 'imxrt.c', - 'kinetis.c', - 'nxpke04.c', - 's32k3xx.c', - ), - compile_args: ['-DCONFIG_NXP=1'], - dependencies: target_cortexm, -) - -target_puya = declare_dependency( - sources: files('puya.c'), - compile_args: ['-DCONFIG_PUYA=1'], - dependencies: target_cortexm, -) - -target_renesas_ra = declare_dependency( - sources: files('renesas_ra.c'), - compile_args: ['-DCONFIG_RA=1'], - dependencies: target_cortexm, -) - -target_renesas_rz = declare_dependency( - sources: files('renesas_rz.c'), - compile_args: ['-DCONFIG_RZ=1'], - dependencies: target_cortexar, -) - -# If the Cortex-A/R target is not enabled, don't enable Renesas RZ part support -if not is_firmware_build or enabled_targets.contains('cortexar') -target_renesas = [ - target_renesas_ra, - target_renesas_rz, -] -else -target_renesas = target_renesas_ra -endif - -target_rp = declare_dependency( - sources: files( - 'rp2040.c', - 'rp2350.c', - ) + rp2040_stub, - compile_args: ['-DCONFIG_RP=1'], - dependencies: target_cortexm, -) - -target_sam = declare_dependency( - sources: files( - 'sam3x.c', - 'sam4l.c', - 'samd.c', - 'samx5x.c', +targets += { + 'riscv32': declare_dependency( + sources: files('riscv32.c'), + dependencies: riscv_common, + variables: { + 'description': 'RISC-V 32-bit support' + }, + ) +} + +targets += { + 'riscv64': declare_dependency( + sources: files('riscv64.c'), + dependencies: riscv_common, + variables: { + 'description': 'RISC-V 64-bit support' + }, + ) +} + +targets += { + 'apollo3': declare_dependency( + sources: files('apollo3.c'), + compile_args: ['-DCONFIG_APOLLO3=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Ambiq Apollo3 parts' + }, + ) +} + +targets += { + 'ch579': declare_dependency( + sources: files('ch579.c'), + compile_args: ['-DCONFIG_CH579=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'WinChipHead CH579' + }, + ) +} + +targets += { + 'efm': declare_dependency( + sources: files( + 'efm32.c' + ) + efm32_stub, + compile_args: ['-DCONFIG_EFM32=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Energy Micro parts' + }, + ) +} + +targets += { + 'hc32': declare_dependency( + sources: files('hc32l110.c'), + compile_args: ['-DCONFIG_HC32=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'HC32 parts' + }, + ) +} + +targets += { + 'lpc': declare_dependency( + sources: files( + 'lpc11xx.c', + 'lpc15xx.c', + 'lpc17xx.c', + 'lpc40xx.c', + 'lpc43xx.c', + 'lpc546xx.c', + 'lpc55xx.c', + 'lpc_common.c', + ), + compile_args: ['-DCONFIG_LPC=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'LPC series parts' + }, + ) +} + +targets += { + 'nrf': declare_dependency( + sources: files( + 'nrf51.c', + 'nrf54l.c', + 'nrf91.c', + ), + compile_args: ['-DCONFIG_NRF=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'nRF series parts' + }, + ) +} + +targets += { + 'nxp': declare_dependency( + sources: files( + 'imxrt.c', + 'kinetis.c', + 'nxpke04.c', + 's32k3xx.c', + ), + compile_args: ['-DCONFIG_NXP=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Kinetis series parts' + }, + ) +} + +targets += { + 'puya': declare_dependency( + sources: files('puya.c'), + compile_args: ['-DCONFIG_PUYA=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Puya PY32 series parts' + }, + ) +} + +targets += { + 'renesas_ra': declare_dependency( + sources: files('renesas_ra.c'), + compile_args: ['-DCONFIG_RA=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Renesas RA parts' + }, ), - compile_args: ['-DCONFIG_SAM=1'], - dependencies: target_cortexm, -) + 'renesas_rz': declare_dependency( + sources: files('renesas_rz.c'), + compile_args: ['-DCONFIG_RZ=1'], + dependencies: targets['cortexar'], + variables: { + 'description': 'Renesas RZ parts' + }, + ) +} +targets += { + 'renesas': declare_dependency( + dependencies: [targets['renesas_ra'], targets['renesas_rz']], + variables: { + 'description': 'Renesas parts (RA + RZ)' + }, + ) +} + +targets += { + 'rp': declare_dependency( + sources: files( + 'rp2040.c', + 'rp2350.c', + ) + rp2040_stub, + compile_args: ['-DCONFIG_RP=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Raspberry Pi MCUs (RP2040, RP2350)' + }, + ) +} + +targets += { + 'sam': declare_dependency( + sources: files( + 'sam3x.c', + 'sam4l.c', + 'samd.c', + 'samx5x.c', + ), + compile_args: ['-DCONFIG_SAM=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'ATSAM series parts' + }, + ) +} -target_stm_common = declare_dependency( +stm_common = declare_dependency( sources: files( 'stm32_common.c', ) ) -target_stm32f1_deps = [target_cortexm, target_stm_common] -# If the 32-bit RISC-V target is not enabled, don't enable GD32VF103 support -if not is_firmware_build or enabled_targets.contains('riscv32') - target_stm32f1_deps += [target_riscv32] -endif - -target_stm32f1 = declare_dependency( - sources: files( - 'stm32f1.c', - ), - dependencies: target_stm32f1_deps, -) - -target_stm32f4 = declare_dependency( - sources: files( - 'stm32f4.c', - ), - dependencies: [target_cortexm, target_stm_common], -) - -target_ch32 = declare_dependency( - sources: files( - 'ch32f1.c', - ), - compile_args: ['-DCONFIG_CH32=1'], - dependencies: target_stm32f1, -) - -target_ch32v = declare_dependency( - sources: files( - 'ch32vx.c', - ), - dependencies: target_riscv32, -) - -target_stm = declare_dependency( - sources: files( - 'stm32g0.c', - 'stm32h5.c', - 'stm32h7.c', - 'stm32l0.c', - 'stm32l4.c', - 'stm32mp15.c', - 'stm32wb0.c', +targets += { + 'stm32f1': declare_dependency( + sources: files( + 'stm32f1.c', + ), + dependencies: [targets['cortexm'], stm_common], + variables: { + 'description': 'STM32F1 parts' + }, ), - compile_args: ['-DCONFIG_STM=1'], - dependencies: [target_cortexm, target_stm_common, target_stm32f1, target_stm32f4], -) - -target_gd32 = declare_dependency( - dependencies: [target_stm32f1, target_stm32f4], - compile_args: ['-DCONFIG_GD32=1'], -) - -target_mm32 = declare_dependency( - dependencies: target_stm32f1, - compile_args: ['-DCONFIG_MM32=1'], -) - -target_at32f4 = declare_dependency( - sources: files( - 'at32f43x.c', + 'stm32f4': declare_dependency( + sources: files( + 'stm32f4.c', + ), + dependencies: [targets['cortexm'], stm_common], + variables: { + 'description': 'STM32F4 parts' + }, + ) +} + +targets += { + 'ch32': declare_dependency( + sources: files( + 'ch32f1.c', + ), + compile_args: ['-DCONFIG_CH32=1'], + dependencies: targets['stm32f1'], + variables: { + 'description': 'WinChipHead CH32 ARM Cortex parts' + }, ), - compile_args: ['-DCONFIG_AT32=1'], - dependencies: [target_cortexm, target_stm_common] -) - -target_ti = declare_dependency( - sources: files( - 'lmi.c', - 'msp432e4.c', - 'msp432p4.c', - 'mspm0.c' - ) + lmi_stub, - compile_args: ['-DCONFIG_TI=1'], - dependencies: target_cortexm, -) - -target_xilinx = declare_dependency( - sources: files( - 'zynq7000.c', + 'ch32v': declare_dependency( + sources: files( + 'ch32vx.c', + ), + dependencies: targets['riscv32'], + variables: { + 'description': 'WinChipHead CH32 RISC-V parts' + }, + ) +} + +targets += { + 'stm': declare_dependency( + sources: files( + 'stm32g0.c', + 'stm32h5.c', + 'stm32h7.c', + 'stm32l0.c', + 'stm32l4.c', + 'stm32mp15.c', + 'stm32wb0.c', + ), + compile_args: ['-DCONFIG_STM=1'], + dependencies: [targets['cortexm'], stm_common, targets['stm32f1'], targets['stm32f4']], + variables: { + 'description': 'STM32 parts' + }, + ) +} + +targets += { + 'gd32': declare_dependency( + dependencies: [targets['stm32f1'], targets['stm32f4']], + compile_args: ['-DCONFIG_GD32=1'], + variables: { + 'description': 'GigaDevice parts' + }, ), - dependencies: target_cortexar, - compile_args: ['-DCONFIG_XILINX=1'], -) + 'gd32_rv': declare_dependency( + dependencies: [targets['riscv32'], targets['stm32f1'], targets['stm32f4']], + compile_args: ['-DCONFIG_GD32=1'], + variables: { + 'description': 'GigaDevice Risc-V parts' + }, + ) +} + +targets += { + 'mm32': declare_dependency( + dependencies: targets['stm32f1'], + compile_args: ['-DCONFIG_MM32=1'], + variables: { + 'description': 'MindMotion parts' + }, + ) +} + +targets += { + 'at32f4': declare_dependency( + sources: files( + 'at32f43x.c', + ), + compile_args: ['-DCONFIG_AT32=1'], + dependencies: [targets['cortexm'], stm_common], + variables: { + 'description': 'Arterytek parts' + }, + ) +} + +targets += { + 'ti': declare_dependency( + sources: files( + 'lmi.c', + 'msp432e4.c', + 'msp432p4.c', + 'mspm0.c' + ) + lmi_stub, + compile_args: ['-DCONFIG_TI=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Texas Instruments parts' + }, + ) +} + +targets += { + 'xilinx': declare_dependency( + sources: files( + 'zynq7000.c', + ), + dependencies: targets['cortexar'], + compile_args: ['-DCONFIG_XILINX=1'], + variables: { + 'description': 'Xilinx parts' + }, + ) +} if is_firmware_build # Convert targets option list into a list of dependencies - enabled_target_deps = [] - foreach target : enabled_targets - enabled_target_deps += get_variable(f'target_@target@') + enabled_bmd_targets = [] + foreach target_name : get_option('targets') + enabled_bmd_targets += targets[target_name] endforeach - # Check if we should enable the RISC-V Debug remote protocol acceleration and do so if required - enable_riscv_accel = get_option('enable_riscv_accel') - if enable_riscv_accel - enabled_target_deps += declare_dependency( - compile_args: ['-DCONFIG_RISCV_ACCEL=1'], - dependencies: riscv_jtag_dtm, - ) - endif - - summary( - 'RISC-V acceleration', - enable_riscv_accel, - bool_yn: true, - section: 'Remote Protocol', + # Check that at least one target is enabled + assert( + enabled_bmd_targets.length() > 0, + '''No debug targets enabled, please enable at least one target to build. + See the 'targets' option for a list of available targets. + ''', ) # BMD target dependency bmd_targets = declare_dependency( include_directories: target_common_includes, sources: target_common_sources, - dependencies: enabled_target_deps, + dependencies: enabled_bmd_targets, ) endif -libbmd_target_deps = [ - # Enable all architectures for libbmd - target_cortexar, - target_cortexm, - target_cortexa_armv8, - target_riscv32, - target_riscv64, - # Enable all targets for libbmd - target_apollo3, - target_at32f4, - target_ch32, - target_ch32v, - target_ch579, - target_efm, - target_gd32, - target_hc32, - target_lpc, - target_mm32, - target_nrf, - target_nxp, - target_puya, - target_renesas_ra, - target_renesas_rz, - target_rp, - target_sam, - target_stm, - target_ti, - target_xilinx, -] - -# Define the libbmd target dependency +# Define the libbmd target dependency, enable all architectures and targets +all_targets = [] +foreach target_name, target_dep : targets + all_targets += target_dep +endforeach libbmd_targets = declare_dependency( include_directories: target_common_includes, sources: target_common_sources, - dependencies: libbmd_target_deps, + dependencies: all_targets, ) if is_firmware_build # Build a dictionary of the targets that have been selected for the firmware build - target_states = {} - foreach target_id, target_name : target_names - target_states += {target_name: target_id in enabled_targets} + target_summary = {} + foreach target_name, target_dep : targets + # Get the target description and add the enabled status to the summary + target_description = target_dep.get_variable('description') + target_summary += {target_description: target_dep in enabled_bmd_targets} endforeach # Include the target enable list in the summary output summary( - target_states, + target_summary, bool_yn: true, section: 'Targets', )