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bluepillplus: Add chip detection via CoreSight ROM tables
1 parent b0bb15e commit ff7aa7c

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+98
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‎src/platforms/bluepillplus/platform.c‎

Lines changed: 98 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,102 @@ static void rcc_set_usbpre_gd32f30x(uint32_t usbpre)
8888
#endif
8989
}
9090

91+
/* ROM table CIDR values */
92+
#define CIDR0_OFFSET 0xff0U /* DBGCID0 */
93+
#define CIDR1_OFFSET 0xff4U /* DBGCID1 */
94+
#define CIDR2_OFFSET 0xff8U /* DBGCID2 */
95+
#define CIDR3_OFFSET 0xffcU /* DBGCID3 */
96+
97+
#define PIDR0_OFFSET 0xfe0U /* DBGPID0 */
98+
#define PIDR1_OFFSET 0xfe4U /* DBGPID1 */
99+
#define PIDR2_OFFSET 0xfe8U /* DBGPID2 */
100+
#define PIDR3_OFFSET 0xfecU /* DBGPID3 */
101+
#define PIDR4_OFFSET 0xfd0U /* DBGPID4 */
102+
#define PIDR5_OFFSET 0xfd4U /* DBGPID5 (Reserved) */
103+
#define PIDR6_OFFSET 0xfd8U /* DBGPID6 (Reserved) */
104+
#define PIDR7_OFFSET 0xfdcU /* DBGPID7 (Reserved) */
105+
106+
#define ROMTABLE_BASE 0xe00ff000U
107+
108+
static uint64_t coresight_romtable_pidr(void)
109+
{
110+
uint8_t pidr[8] = {0};
111+
uint64_t pid64 = 0;
112+
113+
/* Pack bytes from sparse Product ID registers */
114+
pidr[0] = *(const uint32_t *)(ROMTABLE_BASE + PIDR0_OFFSET);
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pidr[1] = *(const uint32_t *)(ROMTABLE_BASE + PIDR1_OFFSET);
116+
pidr[2] = *(const uint32_t *)(ROMTABLE_BASE + PIDR2_OFFSET);
117+
pidr[3] = *(const uint32_t *)(ROMTABLE_BASE + PIDR3_OFFSET);
118+
pidr[4] = *(const uint32_t *)(ROMTABLE_BASE + PIDR4_OFFSET);
119+
120+
memcpy(&pid64, pidr, 8);
121+
return pid64;
122+
}
123+
124+
static uint32_t coresight_romtable_cidr_check(void)
125+
{
126+
uint8_t cidr[4] = {0};
127+
uint32_t cid32 = 0;
128+
/* Pack bytes from sparse Component ID registers */
129+
cidr[0] = *(const uint32_t *)(ROMTABLE_BASE + CIDR0_OFFSET);
130+
cidr[1] = *(const uint32_t *)(ROMTABLE_BASE + CIDR1_OFFSET);
131+
cidr[2] = *(const uint32_t *)(ROMTABLE_BASE + CIDR2_OFFSET);
132+
cidr[3] = *(const uint32_t *)(ROMTABLE_BASE + CIDR3_OFFSET);
133+
134+
memcpy(&cid32, cidr, 4);
135+
return cid32;
136+
}
137+
138+
static void platform_detect_variant(void)
139+
{
140+
/* Detect platform chip */
141+
const uint32_t device_id = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK;
142+
const uint32_t cpu_id = SCB_CPUID & SCB_CPUID_PARTNO;
143+
const uint64_t romtable_pidr = coresight_romtable_pidr();
144+
const uint32_t romtable_cidr = coresight_romtable_cidr_check();
145+
/* STM32F103CB: 0x410 (Medium density) is readable as 0x000 (errata) without debugger. So default to 72 MHz. */
146+
const struct rcc_clock_scale *clock = &rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ];
147+
/*
148+
* Pick one of 72/96/120 MHz PLL configs.
149+
* Disable USBD clock (after bootloaders)
150+
* then change USBDPSC[1:0] the CK_USBD prescaler
151+
* and finally enable PLL.
152+
*/
153+
if ((device_id == 0x410 || device_id == 0x000) && cpu_id == 0xc230 && SCB_CPUID == 0x411fc231U) {
154+
/* STM32F103CB: 0x410 (Medium density), 0x411fc231 (Cortex-M3 r1p1) */
155+
if (romtable_cidr == 0xb105100dU && romtable_pidr == 0xa0410) {
156+
/* STM32F103: Manufacturer 020 Partno 410 (PIDR = 0x00000a0410) */
157+
clock = &rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ];
158+
}
159+
}
160+
161+
if (device_id == 0x410 && cpu_id == 0xc230 && SCB_CPUID == 0x412fc231U) {
162+
/* GD32F103CB: 0x410 (Medium Density), 0x412fc231 (Cortex-M3 r2p1) */
163+
if (romtable_cidr == 0xb105100dU && romtable_pidr == 0x07000d1f64ULL) {
164+
/* GD32F103: Manufacturer 751 Partno f64 (PIDR = 0x07000d1f64) */
165+
clock = &rcc_hse_config_hse8_96mhz;
166+
rcc_periph_clock_disable(RCC_USB);
167+
/* Set 96/2=48MHz USB divisor before enabling PLL */
168+
rcc_set_usbpre_gd32f30x(RCC_CFGR_USBPRE_PLL_CLK_DIV2);
169+
}
170+
}
171+
172+
if (device_id == 0x414 && cpu_id == 0xc240 && SCB_CPUID == 0x410fc241) {
173+
/* GD32F303CC: High density, 0x410fc241 (Cortex-M4F r0p1) */
174+
if (romtable_cidr == 0xb105100dU && romtable_pidr == 0x07000d1050ULL) {
175+
/* GD32F303: Manufacturer 751 Partno 050 (PIDR = 0x07000d1050) */
176+
clock = &rcc_hse_config_hse8_120mhz;
177+
rcc_periph_clock_disable(RCC_USB);
178+
/* Set 120/2.5=48MHz USB divisor before enabling PLL */
179+
rcc_set_usbpre_gd32f30x(RCC_CFGR_USBPRE_PLL_CLK_DIV2_5);
180+
}
181+
}
182+
183+
/* Enable PLL */
184+
rcc_clock_setup_pll(clock);
185+
}
186+
91187
void platform_request_boot(void)
92188
{
93189
magic[0] = BOOTMAGIC0;
@@ -116,38 +212,8 @@ void platform_init(void)
116212
rcc_periph_clock_enable(SWO_DMA_CLK);
117213
#endif
118214

119-
/* Detect platform chip */
120-
const uint32_t device_id = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK;
121-
const uint32_t cpu_id = SCB_CPUID & SCB_CPUID_PARTNO;
122-
/* STM32F103CB: 0x410 (Medium density) is readable as 0x000 (errata) without debugger. So default to 72 MHz. */
123-
const struct rcc_clock_scale *clock = &rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ];
124-
/*
125-
* Pick one of 72/96/120 MHz PLL configs.
126-
* Disable USBD clock (after bootloaders)
127-
* then change USBDPSC[1:0] the CK_USBD prescaler
128-
* and finally enable PLL.
129-
*/
130-
if ((device_id == 0x410 || device_id == 0x000) && cpu_id == 0xc230 && SCB_CPUID == 0x411fc231) {
131-
/* STM32F103CB: 0x410 (Medium density), 0x411fc231 (Cortex-M3 r1p1) */
132-
clock = &rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ];
133-
}
134-
if (device_id == 0x410 && cpu_id == 0xc230 && SCB_CPUID == 0x412fc231) {
135-
/* GD32F103CB: 0x410 (Medium Density), 0x412fc231 (Cortex-M3 r2p1) */
136-
clock = &rcc_hse_config_hse8_96mhz;
137-
rcc_periph_clock_disable(RCC_USB);
138-
/* Set 96/2=48MHz USB divisor before enabling PLL */
139-
rcc_set_usbpre_gd32f30x(RCC_CFGR_USBPRE_PLL_CLK_DIV2);
140-
}
141-
if (device_id == 0x414 && cpu_id == 0xc240 && SCB_CPUID == 0x410fc241) {
142-
/* GD32F303CC: 0x414 (High density) 0x410fc241 (Cortex-M4F r0p1) */
143-
clock = &rcc_hse_config_hse8_120mhz;
144-
rcc_periph_clock_disable(RCC_USB);
145-
/* Set 120/2.5=48MHz USB divisor before enabling PLL */
146-
rcc_set_usbpre_gd32f30x(RCC_CFGR_USBPRE_PLL_CLK_DIV2_5);
147-
}
148-
149-
/* Enable PLL */
150-
rcc_clock_setup_pll(clock);
215+
/* Detect which chip we're running on, and set Hclk as legally fast as possible */
216+
platform_detect_variant();
151217

152218
gpio_set_mode(TMS_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_INPUT_FLOAT, TMS_PIN);
153219
gpio_set_mode(TCK_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_INPUT_FLOAT, TCK_PIN);

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