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bluepillplus: Add support for SPI1
* WeActStudio.BluePill-Plus boards have a DNF SOIC-8 footprint for 25-series SPI NOR flash, wired to PA4/5/6/7. * Add the pin mappings regardless of the platform flavour.
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-8
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2 files changed

+61
-8
lines changed

src/platforms/bluepillplus/platform.c

Lines changed: 52 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include <libopencm3/cm3/scb.h>
3030
#include <libopencm3/stm32/rcc.h>
3131
#include <libopencm3/stm32/dbgmcu.h>
32+
#include <libopencm3/stm32/spi.h>
3233

3334
volatile uint32_t magic[2] __attribute__((section(".noinit")));
3435

@@ -268,26 +269,69 @@ const char *platform_target_voltage(void)
268269

269270
bool platform_spi_init(const spi_bus_e bus)
270271
{
271-
(void)bus;
272-
return false;
272+
uint32_t controller = 0;
273+
if (bus == SPI_BUS_INTERNAL) {
274+
/* Set up onboard flash SPI GPIOs: PA5/6/7 as SPI1 in AF5, PA4 as nCS output push-pull */
275+
gpio_set_mode(OB_SPI_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
276+
OB_SPI_SCLK | OB_SPI_MISO | OB_SPI_MOSI);
277+
gpio_set_mode(OB_SPI_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, OB_SPI_CS);
278+
/* Deselect the targeted peripheral chip */
279+
gpio_set(OB_SPI_PORT, OB_SPI_CS);
280+
281+
rcc_periph_clock_enable(RCC_SPI1);
282+
rcc_periph_reset_pulse(RST_SPI1);
283+
controller = OB_SPI;
284+
} else
285+
return false;
286+
287+
/* Set up hardware SPI: master, PCLK/8, Mode 0, 8-bit MSB first */
288+
spi_init_master(controller, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
289+
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
290+
spi_enable(controller);
291+
return true;
273292
}
274293

275294
bool platform_spi_deinit(const spi_bus_e bus)
276295
{
277-
(void)bus;
278-
return false;
296+
if (bus == SPI_BUS_INTERNAL) {
297+
spi_disable(OB_SPI);
298+
/* Gate SPI1 APB clock */
299+
rcc_periph_clock_disable(RCC_SPI1);
300+
/* Unmap GPIOs */
301+
gpio_set_mode(
302+
OB_SPI_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, OB_SPI_SCLK | OB_SPI_MISO | OB_SPI_MOSI | OB_SPI_CS);
303+
return true;
304+
} else
305+
return false;
279306
}
280307

281308
bool platform_spi_chip_select(const uint8_t device_select)
282309
{
283-
(void)device_select;
284-
return false;
310+
const uint8_t device = device_select & 0x7fU;
311+
const bool select = !(device_select & 0x80U);
312+
uint32_t port;
313+
uint16_t pin;
314+
switch (device) {
315+
case SPI_DEVICE_INT_FLASH:
316+
port = OB_SPI_CS_PORT;
317+
pin = OB_SPI_CS;
318+
break;
319+
default:
320+
return false;
321+
}
322+
gpio_set_val(port, pin, select);
323+
return true;
285324
}
286325

287326
uint8_t platform_spi_xfer(const spi_bus_e bus, const uint8_t value)
288327
{
289-
(void)bus;
290-
return value;
328+
switch (bus) {
329+
case SPI_BUS_INTERNAL:
330+
return spi_xfer(OB_SPI, value);
331+
break;
332+
default:
333+
return 0U;
334+
}
291335
}
292336

293337
int platform_hwversion(void)

src/platforms/bluepillplus/platform.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,15 @@ extern bool debug_bmp;
168168
#define SWO_PIN GPIO7
169169
#endif /* PLATFORM_HAS_TRACESWO */
170170

171+
/* SPI1: PA4/5/6/7 to onboard w25q64 */
172+
#define OB_SPI SPI1
173+
#define OB_SPI_PORT GPIOA
174+
#define OB_SPI_SCLK GPIO5
175+
#define OB_SPI_MISO GPIO6
176+
#define OB_SPI_MOSI GPIO7
177+
#define OB_SPI_CS_PORT GPIOA
178+
#define OB_SPI_CS GPIO4
179+
171180
/* One active-low button labeled "KEY" */
172181
#define USER_BUTTON_PORT GPIOA
173182
#define USER_BUTTON_PIN GPIO0

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