|
29 | 29 | #include <libopencm3/cm3/scb.h> |
30 | 30 | #include <libopencm3/stm32/rcc.h> |
31 | 31 | #include <libopencm3/stm32/dbgmcu.h> |
| 32 | +#include <libopencm3/stm32/spi.h> |
32 | 33 |
|
33 | 34 | volatile uint32_t magic[2] __attribute__((section(".noinit"))); |
34 | 35 |
|
@@ -268,26 +269,69 @@ const char *platform_target_voltage(void) |
268 | 269 |
|
269 | 270 | bool platform_spi_init(const spi_bus_e bus) |
270 | 271 | { |
271 | | - (void)bus; |
272 | | - return false; |
| 272 | + uint32_t controller = 0; |
| 273 | + if (bus == SPI_BUS_INTERNAL) { |
| 274 | + /* Set up onboard flash SPI GPIOs: PA5/6/7 as SPI1 in AF5, PA4 as nCS output push-pull */ |
| 275 | + gpio_set_mode(OB_SPI_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, |
| 276 | + OB_SPI_SCLK | OB_SPI_MISO | OB_SPI_MOSI); |
| 277 | + gpio_set_mode(OB_SPI_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, OB_SPI_CS); |
| 278 | + /* Deselect the targeted peripheral chip */ |
| 279 | + gpio_set(OB_SPI_PORT, OB_SPI_CS); |
| 280 | + |
| 281 | + rcc_periph_clock_enable(RCC_SPI1); |
| 282 | + rcc_periph_reset_pulse(RST_SPI1); |
| 283 | + controller = OB_SPI; |
| 284 | + } else |
| 285 | + return false; |
| 286 | + |
| 287 | + /* Set up hardware SPI: master, PCLK/8, Mode 0, 8-bit MSB first */ |
| 288 | + spi_init_master(controller, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, |
| 289 | + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); |
| 290 | + spi_enable(controller); |
| 291 | + return true; |
273 | 292 | } |
274 | 293 |
|
275 | 294 | bool platform_spi_deinit(const spi_bus_e bus) |
276 | 295 | { |
277 | | - (void)bus; |
278 | | - return false; |
| 296 | + if (bus == SPI_BUS_INTERNAL) { |
| 297 | + spi_disable(OB_SPI); |
| 298 | + /* Gate SPI1 APB clock */ |
| 299 | + rcc_periph_clock_disable(RCC_SPI1); |
| 300 | + /* Unmap GPIOs */ |
| 301 | + gpio_set_mode( |
| 302 | + OB_SPI_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, OB_SPI_SCLK | OB_SPI_MISO | OB_SPI_MOSI | OB_SPI_CS); |
| 303 | + return true; |
| 304 | + } else |
| 305 | + return false; |
279 | 306 | } |
280 | 307 |
|
281 | 308 | bool platform_spi_chip_select(const uint8_t device_select) |
282 | 309 | { |
283 | | - (void)device_select; |
284 | | - return false; |
| 310 | + const uint8_t device = device_select & 0x7fU; |
| 311 | + const bool select = !(device_select & 0x80U); |
| 312 | + uint32_t port; |
| 313 | + uint16_t pin; |
| 314 | + switch (device) { |
| 315 | + case SPI_DEVICE_INT_FLASH: |
| 316 | + port = OB_SPI_CS_PORT; |
| 317 | + pin = OB_SPI_CS; |
| 318 | + break; |
| 319 | + default: |
| 320 | + return false; |
| 321 | + } |
| 322 | + gpio_set_val(port, pin, select); |
| 323 | + return true; |
285 | 324 | } |
286 | 325 |
|
287 | 326 | uint8_t platform_spi_xfer(const spi_bus_e bus, const uint8_t value) |
288 | 327 | { |
289 | | - (void)bus; |
290 | | - return value; |
| 328 | + switch (bus) { |
| 329 | + case SPI_BUS_INTERNAL: |
| 330 | + return spi_xfer(OB_SPI, value); |
| 331 | + break; |
| 332 | + default: |
| 333 | + return 0U; |
| 334 | + } |
291 | 335 | } |
292 | 336 |
|
293 | 337 | int platform_hwversion(void) |
|
0 commit comments