adiv5_jtag: Restore lost JTAG-DP state across resets

* In some targets like AT32F403A, a nRST falling edge behaves like TRST.
  IR is loaded with IDCODE. Next transaction expects DPACC but gets a 8974008e:7.
* Mangle internal JTAG IR cache to BYPASS state so that daisy-chaining works.
  For the active/attached target, BMD logic should run through Capture-IR.
* Nothing is needed in SWD transport, so avoid calling a null pointer.

Author: ALTracer

src/target/adiv5.h

@@ -294,5 +294,6 @@ uint32_t adiv5_jtag_read(adiv5_debug_port_s *dp, uint16_t addr);
 uint32_t adiv5_jtag_raw_access(adiv5_debug_port_s *dp, uint8_t rnw, uint16_t addr, uint32_t value);
 uint32_t adiv5_jtag_clear_error(adiv5_debug_port_s *dp, bool protocol_recovery);
 void adiv5_jtag_abort(adiv5_debug_port_s *dp, uint32_t abort);
+void adiv5_jtag_ensure_idle(adiv5_debug_port_s *dp);
 
 #endif /* TARGET_ADIV5_H */

src/target/adiv5_internal.h

@@ -203,6 +203,7 @@ struct adiv5_debug_port {
 	uint32_t (*error)(adiv5_debug_port_s *dp, bool protocol_recovery);
 	uint32_t (*low_access)(adiv5_debug_port_s *dp, uint8_t RnW, uint16_t addr, uint32_t value);
 	void (*abort)(adiv5_debug_port_s *dp, uint32_t abort);
+	void (*ensure_idle)(adiv5_debug_port_s *dp);
 
 #if CONFIG_BMDA == 1
 	void (*ap_regs_read)(adiv5_access_port_s *ap, void *data);

src/target/adiv5_jtag.c

@@ -55,6 +55,7 @@ void adiv5_jtag_dp_handler(const uint8_t dev_index)
 	dp->low_access = adiv5_jtag_raw_access;
 	dp->error = adiv5_jtag_clear_error;
 	dp->abort = adiv5_jtag_abort;
+	dp->ensure_idle = adiv5_jtag_ensure_idle;
 #if CONFIG_BMDA == 1
 	bmda_jtag_dp_init(dp);
 #endif
@@ -175,3 +176,14 @@ void adiv5_jtag_abort(adiv5_debug_port_s *dp, uint32_t abort)
 	jtag_dev_write_ir(dp->dev_index, IR_ABORT);
 	jtag_dev_shift_dr(dp->dev_index, NULL, (const uint8_t *)&request, 35);
 }
+
+void adiv5_jtag_ensure_idle(adiv5_debug_port_s *dp)
+{
+	/*
+	 * On devices where nRST pulls TRST, the JTAG-DP's IR is reset
+	 * from DPACC/APACC to IDCODE. We want BYPASS in case of daisy-chaining.
+	 */
+	jtag_devs[dp->dev_index].current_ir = 0xffU;
+	/* Go from TLR to RTI. */
+	jtagtap_return_idle(1);
+}

src/target/adiv5_swd.c

@@ -172,6 +172,7 @@ bool adiv5_swd_scan(const uint32_t targetid)
 	dp->low_access = adiv5_swd_raw_access;
 	dp->error = adiv5_swd_clear_error;
 	dp->abort = adiv5_swd_abort;
+	dp->ensure_idle = NULL;
 
 #if CONFIG_BMDA == 0
 	swdptap_init();

src/target/cortexm.c

@@ -784,6 +784,11 @@ static void cortexm_reset(target_s *const target)
 		platform_delay(10);
 	}
 
+	adiv5_access_port_s *ap = cortex_ap(target);
+	adiv5_debug_port_s *dp = ap->dp;
+	if (dp->ensure_idle)
+		dp->ensure_idle(dp);
+
 	/* Check if the reset succeeded */
 	const uint32_t status = target_mem32_read32(target, CORTEXM_DHCSR);
 	if (!(status & CORTEXM_DHCSR_S_RESET_ST)) {
@@ -792,6 +797,8 @@ static void cortexm_reset(target_s *const target)
 		 * Trigger reset by AIRCR.
 		 */
 		target_mem32_write32(target, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
+		if (dp->ensure_idle)
+			dp->ensure_idle(dp);
 	}
 
 	/* If target needs to do something extra (see Atmel SAM4L for example) */